Abstract: Data, such as data received by a memory I/O from a memory unit in a DDR SDRAM system, is captured using a trigger signal, which may be a non free-running clock signal such as a DQS signal in a DDR SDRAM system, and is transferred to a host system, which may be part of an ASIC, using the host system's clock. The memory I/O includes a data capture register that latches the data received from the memory unit using DQS. The memory I/O also includes a FIFO buffer that latches the data output by the data capture register using a delayed version of DQS. A single edge of the delayed DQS is available to the FIFO for latching each set of data that corresponds to a single pulse of DQS. The FIFO transfers the data to the host system using the host system's clock, which represents a different clock domain than DQS.

Abstract: A system and method for rapid processing of scene-graph-based data and/or programs using a render bin is disclosed. In one embodiment, the system may be configured to generate a plurality of structures and thread that manage the data originally received as part of the scene graph. The structures and threads may be configured to convey information about state changes through the use of messaging. The system may include support for messaging between threads, messaging with time and/or event stamps, epochs to ensure consistency, and ancillary structures such as render-bins, geometry structures, and rendering environment structures. One of the structures may be a render bin that may be used to implement parallel rendering.

Abstract: A system and method for cluster-sensitive sticky load balancing of server workload may include a load balancer receiving an initial request from a client. A session may be initiated in response to receiving the request. The load balancer may relay the initial request to a selected node, where the selected node may be part of a cluster of multiple nodes. Upon receiving a subsequent request pertaining to the session initiated by the initial request, the load balancer may determine if the selected node is active. If the selected node is active, the load balancer may relay the subsequent request to the selected node. If the selected node is not active, the load balancer may determine for which cluster the selected node was a member, and relay the subsequent request to another node in that same cluster.

Abstract: An apparatus for adding a first value and a second value each including a plurality of bits includes combiner units, a carry creation unit and summation units. Bits corresponding to bit positions of the first and the second value form respective columns. Each of the combiner units may provide a generate and propagate bit pair in response to receiving respective bits of the first and the second value which correspond to a plurality of the respective columns. The carry creation unit may create an ordered plurality of carry bits each corresponding to one or more of the generate and propagate bit pairs. Each of the summation units may generate a plurality of sum bits in response to receiving the respective bits of the first and the second value which correspond to the plurality of respective columns.

Abstract: A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.

Abstract: One embodiment of the present invention provides a system that uses value speculation to break constraining dependencies in loops. The system operates by first identifying a loop within a computer program, and then identifying a dependency on a long-latency operation within the loop that is likely to constrain execution of the loop. Next, the system breaks the dependency by modifying the loop to predict a value that will break the dependency, and then using the predicted value to speculatively execute subsequent loop instructions.

Abstract: A mechanism for replicating and maintaining files in a space-efficient manner is disclosed. In one embodiment, a current file is replicated by associating the data blocks of the current file with both the current file and a new file. The new file and the current files are separate and distinct from each other. Data blocks remain shared until the content of one file is modified. Only the data blocks affected by the modification are duplicated. The two files share the unchanged data blocks, but both files are each associated with additional data blocks that reflect the modification. Reference values are used to track how many files are associated with each data block. In another embodiment, a file descriptor is linked to a filename at the request of a user or application. The present invention avoids needless duplication of the same data blocks among copies of a file.

Abstract: A computer system includes a processor capable of executing a plurality of N threads of instructions, N being an integer greater than one, with a set of global registers visible to each of the plurality of threads and a plurality of busy bit memory elements used to signal whether or not a register is in use by a thread. The processor includes logic to stall a read from global register if the thread reading the global register is a speculative thread and the busy bits for prior threads are set. The processor might also include a speculative load address memory, into which speculative loads from speculative threads are entered and logic to compare addresses for stores from nonspeculative threads with addressees in the speculative load address memory and invalidate speculative threads corresponding to the speculative load addresses stored in the speculative load address memory.

Abstract: A method for assessing a reliability of a complex component having a plurality of similar subcomponents is described. The complex component is divided into a plurality of component parts, each component part including at least one of the subcomponents. Specification ranges are identified for measured variables within which the component parts are considered to be operating within specification. The complex component is subjected to a reliability test and reliability data is obtained for the component parts by comparing the measured variable for each of the component parts with the specification ranges to determine failure times. A system and machine readable medium embodying program instructions is also provided.

Abstract: A method and apparatus for timely delivery of classes and objects is provided. A header comprising timing information is attached to said classes and/or objects. A “start loading” time and a “load by” time are specified in the header. Other classes and/or objects to be loaded are also specified in the header. Optional compression, security, and/or error resilience schemes are also specified in the header. A process for creating the header and attaching it to a class or object is provided. A process for receiving and processing a class or object with an attached header is provided. Embodiments of the invention allow timely delivery of classes and/or objects over a wide variety of transport mechanisms, including unreliable transport mechanisms and those lacking any guarantees of timely delivery.

Abstract: In accordance with the present invention a method and system for transmitting multibyte characters in a network comprises the steps, performed by a processor, of receiving a set of fixed-length characters; converting each fixed-length character into a multibyte character to determine a length corresponding to the multibyte characters; and transmitting the length and the multibyte characters.

Abstract: The present invention provides a method and apparatus for synchronizing errors in a processor-based system. The method includes forming a sequence of a plurality of language elements, wherein the language elements are adapted to create errors in a system. The method further includes providing the sequence to the system.

Abstract: In one embodiment, a processor comprises an instruction cache and a fetch generator circuit coupled thereto. The fetch generator circuit is configured to generate at least one fetch request to the instruction cache for at least one of the plurality of threads. The fetch generator circuit is also configured to monitor for a plurality of conditions for each thread, wherein each of the plurality of conditions defined to inhibit the thread from being fetched. The fetch generator circuit is configured to speculatively generate a first fetch request for a first thread of the plurality of threads if each thread is inhibited from fetching and the first thread is inhibited from fetching only due to a first predetermined condition of the plurality of conditions. In one particular implementation, the first predetermined condition is a lack of room in a corresponding one of a plurality of instruction buffers.

Abstract: The invention is a method and apparatuses for a console/control concentrator utilizing a location based dynamic coordinate addressing network over a programmable pulse modulated wireless protocol such as TM-UWB™. The physical connections are wireless, which involves adding new hardware, designing TM-UWB™ devices into new devices, adding the software and firmware, the PLT and authentication, a standalone concentrator or the software to emulate a concentrator. The concentrator uses a built-in query language and an internal database to configure and map itself, and all the devices logically attached to it. It also uses the built-in query/language to dynamically add new devices within its range of operation.

Abstract: Method and system for submitting computing jobs in a distributed computing environment including receiving a job request with an instruction to execute a computing job, selecting a job handler for handling the computing job based on selection information and submitting the computing job to the selected job handler. The invention can be embodied in a client unit, thus providing a decentralized distribution of computing jobs and avoiding bottlenecks in the distribution of computing jobs for example in a computing grid.

Abstract: A secure operating system is disclosed in which all code implementing security functionality resides in a security module separate from the operating system code. Calls involving security functions are made using a format or interface which is standardized for all systems. Such a call identifies, inter alia the response and the access mode which are used to identify a call in a two dimensional table which contains a pointer to the needed security functions. In the way security functions are separately compilable and security solving changes can be made by linking in a new security module. Maintenance of security code is separated from maintenance of the underlying operating system.

Abstract: Data exchange system includes at least one portable data processing unit with data communication processing and memory units, the latter including an executive program and one or more application descriptors, each application description including at least one interaction context comprising commands, data elements, data references, procedures, access conditions, and external references; the structure of the data elements and the data references as well as other references is chosen in such a way that a very efficient use of the restricted memory space of e.g. smart cards is obtained.

Abstract: A system and method for precisely identifying an instruction causing a performance-related event is disclosed. The instruction may be detected while in a pipeline stage of a microprocessor preceding a writeback stage and the microprocessor's architectural state may not be updated until after information identifying the instruction is captured. The instruction may be flushed from the pipeline, along with other instructions from the same thread. A hardware trap may be taken when the instruction is detected and/or when an event counter overflows or is within a given range of overflowing. A software trap handler may capture and/or log information identifying the instruction, such as one or more extended address elements, before returning control and initiating a retry of the instruction. The captured and/or logged information may be stored in an event space database usable by a data space profiler to identify performance bottlenecks in the application containing the instruction.

Abstract: We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanisms allow a program to read from a first memory location (called the “flagged” location), and to then continue execution, storing values to zero or more other memory locations such that these stores take effect (i.e., become visible in the memory system) only while the flagged memory location does not change. In some embodiments, the mechanisms further allow the program to determine when the first memory location has changed. We call the proposed mechanisms conditional multi-store synchronization mechanisms and define aspects of an instruction set architecture consistent therewith.

Abstract: In one embodiment, a node comprises at least one processor core and a plurality of coherence units. The processor core is configured to generate an address to access a memory location. The address maps to a first coherence plane of a plurality of coherence planes. Coherence activity is performed within each coherence plane independent of other coherence planes, and a mapping of the address space to the coherence planes is independent of a physical location of the addressed memory in a distributed system memory. Each coherence unit corresponds to a respective coherence plane and is configured to manage coherency for the node and for the respective coherence plane. The coherence units operate independent of each other, and a first coherence unit corresponding to the first coherence plane is coupled to receive the address if external coherency activity is needed to complete the access to the memory location.