Abstract: Multiple-precision hybrid multiplication is a technique that takes advantage of row-wise multiplication and column-wise multiplication. To generate a product for multiple-precision operands, partial products of the multiple-precision operands are accumulated in accordance with a hybrid of column-wise multiplication and row-wise multiplication. The partial products accumulated are of partial rows. The partiality of the row-wise partial products is defined by a parameter.

Abstract: Several methods are provided for applying minimization to computer systems. A unified security profile is created and applied to a computer system. This provides a listing of software packages required to be installed on the computer system. Extraneous files not associated with a required software package are identified. In one method, a software module interposes between calls to filesystem operations and the filesystem. This module allows or denies access to files based on a configuration information source (which is itself based on the unified security profile), the zone from which the access request originates, and the privileges of the user making the request. Reference to each file minimized is removed from the computer system's package manifest. Files thus minimized are neither visible nor accessible to unauthorized entities on the computer system. If the unified security profile of the system is required to change, minimization actions can therefore be reversed.

Abstract: A method and apparatus for conveying test stimulus data from an ATE system to an integrated circuit (IC) via a plesiochronous interconnect. The IC includes a core logic unit and a first receiver coupled to the core logic unit by a first data path. The first receiver includes an input having an interconnect coupled thereto. In a normal mode of operation, the first receiver is configured to receive data transmitted plesiochronously over the interconnect and to convey the data, via the first data path, to the core logic unit. The integrated circuit also includes a second data path coupled between the core logic unit and the interconnect. In a test mode, the core logic unit is configured to receive test stimulus data conveyed synchronously over the second data path, wherein the test stimulus data is received by the IC from the ATE via the interconnect.

Abstract: In a space incremental garbage collector, delays caused by scanning remembered sets are reduced by scanning the remembered sets mostly concurrently with the operation of the non-collection threads. Before scanning, remembered sets associated with regions in some collection set are “sequestered” (no further insertions are allowed by the non-collection threads or the collector) in order to prevent further changes. Any further changes to these sequestered remembered sets that occur before phase two of the scanning process are then handled by one or more “refinement threads.” Each refinement thread is a thread that can record reference locations in remembered sets, scan entries in collection set remembered sets and update reference location lists for use in the aforementioned second phase of remembered set processing. The refinement threads operate concurrently with the operation of the non-collection threads.

Abstract: A first optical coupler is configured to direct optical signals from an optical fiber onto one or more first optical channels located on a semiconductor chip, wherein the one or more first optical channels have dimensions that are within a specified tolerance of the dimensions of the optical fiber. One or more second optical couplers are configured to direct the optical signals from the one or more first optical channels to one or more second optical channels located on the semiconductor chip, wherein the one or more second optical channels have a specified sub-micron size.

Abstract: One embodiment of the present invention provides a system that facilitates high-bandwidth communication using a flexible bridge. This system includes a chip with an active face upon which active circuitry and signal pads reside, and a second component with a surface upon which active circuitry and/or signal pads reside. A flexible bridge provides high-bandwidth communication between the active face of the chip and the surface of the second component. By matching the wire line size in the flexible bridge to the size of circuits and/or signal pads on the chip and on the second component, the system allows signals to be sent between the circuits on the chip and the second component without having to change the scale of the interconnect, thereby alleviating wireability and bandwidth limitations of conventional chip packaging technologies.

Abstract: A semiconductor die includes proximity connectors proximate to a surface of the semiconductor die. This semiconductor die is configured to communicate signals with another semiconductor die via proximity communication through one or more of the proximity connectors. In particular, the proximity connectors include a first group of proximity connectors that is configured to facilitate determining a first separation between the semiconductor die and the other semiconductor die by comparing coupling capacitances between the semiconductor die and the other semiconductor die. Note that the first group of proximity connectors includes a first proximity connector and a second proximity connector, and the second proximity connector at least partially encloses an in-plane outer edge of the first proximity connector.

Abstract: A technique for coordinating execution of instructions in a processor that allows instructions to execute out-of-order includes decoding a particular instruction that is defined in accordance with an instruction set of the processor. A helper sequence of instructions that corresponds to the particular instruction is then introduced into a stream of executable operations. The corresponding helper sequence includes a first artificial dependency instruction that codes a dependency on a register that is not actually employed as a register source or target for an operation performed by the particular instruction.

Abstract: A method for remote services authentication in an internet hosted environment includes a high level process and functionality for a secure, practical and logically optimized inter-network authentication mechanism by employees, partners and customers of an enterprise into the hosted Internet site. The lightweight authentication and authorization mechanism can be most effectively implemented in Java as part of the application or web server servlet. The method for remote services authentication includes initial secure password establishment, subsequent authentication and authorization, as well as authentication and authorization upon resuming previously run sessions with the hosted server using Internet cookies.

Abstract: A multithreading processor achieves a very large lookahead instruction window by allowing non-sequential fetch and processing of the dynamic instruction stream. A speculative thread is spawned at a specified point in the dynamic instruction stream and the instructions subsequent to the specified point are speculatively executed so that these instructions are fetched and issued out of sequential order. Very minimal modifications to existing processor design of a multithreading processor are required to achieve the very large lookahead instruction window. The modifications include changes to the control logic of the issue unit, only three additional bits in the register scoreboard.

Abstract: One embodiment of the present invention provides a system that facilitates buffering data at a kernel in a computer system, wherein the data is buffered based on the structure of a message contained in the data. The system operates by receiving data at a computer system from an external source. Next, the system buffers the data at a kernel on the computer system. As the system buffers the data, the system also determines if the buffered data constitutes a complete message as defined by a communication protocol. If so, the system forwards the buffered data to an application on the computer system.

Abstract: A microprocessor capable of decoding a plurality of instructions associated with a plurality of threads is disclosed. The microprocessor may comprise a first array comprising a first plurality of microcode operations associated with an instruction from within the plurality, the first array capable of delivering a first predetermined number of microcode operations from the first plurality of microcode operations. The microprocessor may further comprise a second array comprising a second plurality of microcode operations, the second array capable of providing one or more of the second plurality of microcode operations in the event that the instruction decodes into more than the first predetermined number of microcode operations. The microprocessor may further comprise an arbiter coupled between the first and second arrays, where the arbiter may determine which thread from the plurality of threads accesses the second array.

Abstract: A data storage tape cartridge is provided with a combination tape including a data storage tape, an intermediate portion and a leader. A servo track and media information region is provided on the intermediate portion of the tape. The servo track is read by a servo track reader of a data storage apparatus. The media information region is read by the read/write head of the data storage apparatus.

Abstract: A system that includes a host including at least one per-connection data structure and at least one per-processor data structure, wherein the at least one per-connection data structure is associated with a connection, and an offload engine operatively connected to the host. The engine includes offload engine connection registers and functionality to update the at least one per-connection data structures in the host, wherein the offload engine is configured to send and receive network data on the connection, wherein the host and the offload engine communicate using the at least one per-processor data structure, and wherein the offload engine communicates a status of the connection to the host using the offload engine connection registers.

Abstract: A method for processing using a shared file that includes creating a plurality of mmaps between a shared file and a plurality of address spaces, wherein each of the plurality of mmaps maps at least a portion of the shared file to one of the plurality of address spaces, and wherein each of the plurality of address spaces is associated with one of a plurality of processors, transferring, in parallel, data between the shared file and the address spaces using the plurality of mmaps associated with the plurality of address spaces, processing the data in parallel by the plurality of processors to obtain a result, wherein the plurality of processors access data from the plurality of address spaces, and storing the result in the shared memory.

Abstract: In one embodiment of a system and method for positioning a transducer head, the transducer head includes a first group of elements for reading data from or writing data to a set of tracks on a storage medium, and a second group of elements for reading data from or writing data to a set of tracks on a storage medium. A device supplies electrical power to the first group of elements to read data from or write data to a first position on the storage medium, and supplies electrical power to the second group of elements to read data from or write data to a second position on the storage medium different than the first position without coarse movement of the transducer head relative to the storage medium.

Abstract: A re-fetching cache memory improves efficiency of a processor, for example by reducing power consumption and/or increasing performance. When the cache memory is disabled or temporarily used for another purpose, a data portion of the cache memory is flushed, and a tag portion is saved in an archive. In some embodiments, the tag portion operates “in-place” as the archive, and in further embodiments, is placed in a reduced-power mode. In some embodiments, less than the full tag portion is archived. When the cache memory is re-enabled or when the temporary use completes, optionally and/or selectively, the tag portion is repopulated from the archive, and the data portion is re-fetched according to the repopulated tag portion. In some embodiments, less than the full archive is restored. According to various embodiments, processor access to the cache is enabled during one or more of: the saving; the repopulating; and the re-fetching.

Abstract: System and method for providing a binary encoding protocol as an alternative to markup language protocols for Web services. Embodiments may provide a Web services stack with a single API that supports a binary encoding protocol in addition to a markup language protocol. Embodiments may dynamically and transparently switch between the markup language protocol and the binary encoding protocol, for example for communications between servers and clients in a Web services network environment. An exemplary markup language is XML. An exemplary binary encoding protocol that may be used is WS-Fast, which may use Abstract Syntax Notation One (ASN.1) and a mapping from XML Schema to ASN.1 for on-the-wire binary messages. Some embodiments may be implemented as a Java Web services stack that implements WS-Fast as an alternative to XML, while still supporting XML and providing one API to both protocols.

Abstract: A patch or set of patches may be deployed, often to a subset of potentially vulnerable systems, to address a particular vulnerability while providing a facility to monitor and, in some cases, characterize post-patch exploit attempts. Often, such a patch will check for an exploit signature and, if an exploit attempt is detected or suspected, take an appropriate action. For example, the patch may include code to log indicative data or trigger such logging. In some exploitations, the patch may generate or contribute to a warning or advisory regarding an additional target (or targets) of the exploit and, if appropriate, initiate a patch or protective measure for the additional target(s). In some exploitations, the patch may simulate responses or behaviors suggestive (to an attacker) of unpatched code. In some exploitations, the patch may direct an exploit attempt to a service (or simulated service) hosted or executing in an isolated protection domain.

Abstract: A system and method for providing exceptional flow control in protected code through watchpoints is described. Code is generated. The generated code includes a sequence of normal operations and is subject to protection against copying during execution of the generated code. Execution points within the generated code are identified. A watchpoint corresponding to each of the execution points is set. An exception handler associated with each watchpoint is defined and includes operations exceptional to the normal operations sequence that are performed upon a triggering of each watchpoint during execution of the generated code.