Abstract: One embodiment of the present invention provides a system which performs simultaneous speculative threading. The system staffs by executing instructions in normal execution mode using a first thread. Upon encountering a data-dependent stall condition, the first thread generates an architectural checkpoint and commences execution of instructions in execute-ahead mode. During execute-ahead mode, the first thread executes instructions that can be executed and defers instructions that cannot be executed into a deferred queue. When the data dependent stall condition has been resolved, the first thread generates a speculative checkpoint and continues execution in execute-ahead mode. At the same time, the second thread commences execution in a deferred mode. During execution in the deferred mode, the second thread executes instructions deferred by the first thread.

Abstract: Architectural techniques and implementations that defer enforcement of certain delayed control transfer instruction (DCTI) sequencing constraints or conventions to later stages of an execution pipeline are described. In this way, complexity of a processor pipeline front-end (including fetch sequencing) can be simplified, at least in-part, by fetching instructions generally without regard to such constraints or conventions. Instead, enforcement of such sequencing constraints and/or conventions may be deferred to one or more pipeline stages associated with commitment or retirement of instructions. Higher fetch bandwidth may be achieved in some realizations when, for example, DCTI couples are encountered in an execution sequence.

Abstract: A system includes a first and a second network component, and a bridge. The bridge, which resides a Media Access Control (MAC) layer of a host, includes a bridge component, a first virtual network interface card (VNIC) and a second VNIC, wherein the first VNIC is associated with the first network component and the second VNIC is associated with the second network component. Further, the bridge component is configured to send packets received from the first network component to the second network component and to send packets received from the second network component to the first network component.

Abstract: A method for analyzing a target system that includes obtaining a characteristics model, loading the characteristics model into a meta model, obtaining a plurality of characteristics from the target system using a characteristics extractor, wherein each of the plurality of characteristics is associated with the characteristics model, storing each of the plurality of characteristics obtained from the target system in a characteristics store, and analyzing the target system by issuing at least one query to the characteristics store to obtain an analysis result, wherein the issuing the at least one query comprises verifying the at least one query using the meta model.

Abstract: A method for increasing recording format reliability in a tape drive system is disclosed. In one embodiment, the method includes identifying a default media information region (MIR) on a media, wherein the default MIR includes MIR information divided into segments, reading the MIR information, rotating the MIR information into a first rotation MIR information by rotating the segments by one segment; and writing the first rotation MIR information into a first MIR on the media. Other embodiments are also disclosed.

Abstract: A method for contiguously appending data onto media in a tape drive system is disclosed. In one embodiment, the method includes reading existing data recorded on a media, determining an append point on the media, and contiguously appending new data on the media starting at the append point such that any end pad is eliminated and no intermediate pads are resulted. Other embodiments are also disclosed.

Abstract: A method, apparatus and computer program product for a composite component includes a first JSP tag component and a second JSP tag component referenced by the first JSP tag component. The composite component utilizes a renderer in communication with one of the JSP tag components, the renderer providing a result in a predetermined format. A JSP buffer is in communication the renderer, and is used to store the result from the renderer.

Abstract: One embodiment of the present invention provides a system which avoids a live-lock state in a processor that supports speculative-execution. The system starts by issuing instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a launch condition during the execution of an instruction (a “launch instruction”) which causes the processor to enter a speculative-execution mode, the system checks status indicators associated with a forward progress buffer. If the status indicators indicate that the forward progress buffer contains data for the launch instruction, the system resumes normal-execution mode. Upon resumption of normal-execution mode, the system retrieves the data from a data field contained in the forward progress buffer and executes the launch instruction using the retrieved data as input data for the launch instruction. The system next deasserts the status indicators.

Abstract: A method for routing a packet. The method includes receiving the packet from a first network into a network interface card (NIC), where the NIC is operatively connected to a host and the host includes a first virtual network stack and a second virtual network stack. The method further includes sending the packet to a first virtual network stack, where the first virtual network stack includes a first filter, a first network layer, and a first transport layer. In addition, the first filter, the first network layer, and the first transport layer are isolated from the second virtual network stack. If the packet is permitted through the first filter in the first virtual network stack, then the packet is sent to a first virtual NIC.

Abstract: Techniques for interpretation of DVD assembly language programs for television (TV) receivers operating in Java TV environments are provided. The techniques can be used to implement a Java-based command/control enabling system. The Java-based command/control enabling system can be implemented as a Java-based DVD assembly language interpreter which interacts with various modules including video, audio, graphics overlay, and remote control modules. As such, the Java-based command/control enabling systems can provide similar command/control functions as those provided by DVD systems.

Abstract: A distributed shared memory multiprocessor system that supports both fine- and coarse-grained interleaving of the shared memory address space. A ceiling mask sets a boundary between the fine-grain interleaved and coarse-grain interleaved memory regions of the distributed shared memory. A method for satisfying a memory access request in a distributed shared memory subsystem of a multiprocessor system having both fine- and coarse-grain interleaved memory segments. Certain low or high order address bits, depending on whether the memory segment is fine- or coarse-grain interleaved, respectively, are used to determine if the memory address is local to a processor node. A method for setting the ceiling mask of a distributed shared memory multiprocessor system to optimize performance of a first application run on a single node and performance of a second application run on a plurality of nodes.

Abstract: Reducing power consumption in microprocessors for the processing of common values. Common values provided in at least one received operation are encoded into encoded common values having a lower number of bits than the common values prior to encoding. In one aspect, a separate encoding bus is used to provide the encoded common values in various processing of additional received operations in the microprocessor instead of a full-bit bus of the microprocessor, the encoding bus having less bits than the full-bit bus. In another aspect, a result of the operation is predicted based on at least one encoded common value and execution of the operation is bypassed.

Abstract: A system that dynamically refreshes the inputs of a differential receiver. During operation, while a differential transmitter is not transmitting data, the system applies substantially equal voltages to the outputs of the differential transmitter so that the differential voltage on the outputs of the differential transmitter is substantially zero. The system then refreshes the inputs of an associated differential receiver by applying substantially equal voltages to the inputs of the differential receiver so that the differential voltage on the inputs of the differential receiver is substantially zero. The differential transmitter is coupled to the differential receiver through a DC blocking mechanism, which prevents a DC voltage on the differential transmitter from reaching the differential receiver.

Abstract: A method and apparatus is disclosed for determining interconnections of network devices. The network devices are connected together based on a set of general guidelines. A first network device is associated with a power state that is changed. Whether an alteration occurs at a second network device in response to the change in power state of the first network device is identified and stored. The changing of the power state of the first network device may be in response to a third network device and may be performed via a power controller. The alteration at the second network device may be a link becoming hot or the raising of a trap that is set at a switch. Errors are identified by comparing whether an alteration is identified to information in a database. Different types of interconnections may be determined in a series of phases by testing different types of devices.

Abstract: One embodiment of the invention provides apparatus and a method for testing a transmission path across one or more printed circuit boards. According to the method, a test signal is presented at a first location on the transmission path. The test signal is generally low frequency compared to normal data communications on the transmission path. A pickup line is capacitively coupled at a second location to the transmission path. The pickup line is monitored with a detector to see whether or not the test signal is present. If the test signal is not present, it is determined that there is a fault on the transmission path between the first location and the second location.

Abstract: A modified high-speed flip-flop including an input circuit, a smart window circuit, a smart keeper circuit, a pre-charge circuit, a discharge circuit, a slave storage circuit, and an output circuit. Additionally, a circuit including the modified high-speed flip-flop, the circuit also including a non-zero operating voltage provided to the flip-flop, a common voltage provided to the flip-flop, a clock signal input to the flip-flop, a data signal input to the flip-flop wherein the data signal has a high state and a low state, and an output signal from the flip-flop wherein the output signal has a high state and a low state.

Abstract: A method for routing packets includes receiving an outbound packet issued by a first virtual machine, wherein the first virtual machine is located on a host, determining a packet destination associated with the outbound packet, querying a routing table for a routing entry corresponding to the packet destination, wherein the routing table comprises a first routing entry referencing an external host and a second routing entry referencing a second virtual machine, wherein the second virtual machine is located on the host, if the routing entry corresponding to the packet destination is the first routing entry, passing the packet to the external host, and if the routing entry corresponding to the packet destination is the second routing entry, passing the packet to the second virtual machine.

Abstract: A heat sink has a heat spreader structure containing magneto-hydrodynamic fluid. Also, the heat spreader includes a central metallic cylinder and a metal ring screen surrounding the central metallic cylinder. Electrical and magnetic fields induce the magneto-hydrodynamic fluid to undergo a swirling motion. The swirling motion acts as an MHD pump and provides efficient heat dissipation from a heat source contacting the heat spreader. A heat sink spreader has a central metallic cylinder surrounded by a metallic ring screen, and a magneto-hydrodynamic fluid.

Abstract: A method and a system for facilitating garbage collection (GC) operations in a memory-management system that supports both mark-sweep (MS) objects and reference-counted (RC) objects, wherein objects which are frequently modified are classified as MS objects, and objects which are infrequently modified are classified as RC objects. During a marking phase of a GC operation, the system identifies a set of root objects and then marks referents of the root objects. The system then recursively traverses referents of the root objects which are MS objects and while doing so, marks referents of the traversed MS objects. However, if an RC object is encountered during the traversal of an MS object, the system marks the RC object but does not recursively traverse the RC object. In doing so, the system avoids traversing a large number of RC objects which are infrequently modified.

Abstract: One embodiment of the present invention provides a system that supports vector operations on a multi-threaded microprocessor. During operation, the system detects a vector instruction in a program. The system maps this vector instruction onto the thread contexts of the multi-threaded microprocessor. As part of the mapping process, the system splits the vector instruction across a set of threads that execute in parallel and generates a set of instructions for the set of threads. This mapping process allows the vector instruction to be executed efficiently across multiple threads.