Abstract: A method for operating a system comprising multiple resources. The method comprises identifying for each resource a set of one or more failure risks for that resource. For each identified failure risk, a likelihood of failure is combined with an expected resolution time to provide a risk weight for the identified failure risk. For each resource, the risk weights for each failure risk are accumulated to provide an accumulated risk weight for the resource. A resource manager provisions workload across the multiple resources based on the accumulated risk weights for each resource.

Abstract: A system that executes a long transaction in a system with limited transactional hardware resources. During operation, the system executes the long transaction in a non transactional mode, which does not use transactional hardware resources. The system defers stores generated during the long transaction so that the stores are not committed to the architectural state of a processor until the transaction is successfully completed. If the long transaction successfully completes, the system commits the long transaction, which involves performing multiple hardware transactions to commit the deferred stores to the architectural state of the processor.

Abstract: A technique in accordance with one embodiment of the present invention provides introspection support for anonymous and local classes. As a result of the technique, an enclosing class that defines a generic type variable that is not defined within a local or anonymous class that refers to the generic type variable can be determined. According to one embodiment of the invention, when a compiler determines that a particular class is a local or anonymous class, the compiler emits, into the particular class' binary class file, information that indicates which class encloses the particular class. In response to the invocation of a method (described herein) relative to a reflective proxy that corresponds to an enclosed class, information that identifies an enclosing class that encloses the enclosed class is returned. This is so even if the enclosed class is a local or anonymous class.

Abstract: A fan enclosure for a system including one more fans and a system enclosure includes a first pivot removably attached to the system enclosure, a safety compliant fan grill attached to the first pivot rotatably between a natural closed position and a forced open position, and a cam disposed on the safety compliant fan grill. The safety compliant fan grill covers the one or more fans in the natural closed position. The cam is configured to force the safety compliant fan grill into the forced open position when a top cover of the system enclosure is placed in a closed position.

Abstract: A system for debugging applications at resource-constrained virtual machines may include a target device configured to host a lightweight debug agent to obtain debug information from one or more threads of execution at a virtual machine executing at the target device, and a debug controller. The lightweight debug agent may include a plurality of independently deployable modules. The debug controller may be configured to select one or more of the modules for deployment at the virtual machine for a debug session initiated to debug a targeted thread, to deploy the selected modules at the virtual machine for the debug session, and to receive debug information related to the targeted thread from the lightweight debug agent during the session.

Abstract: A system and method for controlling the use by caller objects to a restricted method of a resource object in an object-oriented computing environment are provided in accordance with one embodiment of the invention. The method is based on associating an access-token with a caller object which is to be allowed to access the restricted method and sharing this access-token with the resource object. When subsequent calls to the restricted method are made by a caller object, access is made contingent on the caller object providing the access-token as part of the call procedure. Where no access-token is provided, or an invalid access-token is provided, access to the method is denied or restricted. The method provides protection against innocently made wrong calls to a restricted method by a caller object, for example due to coding errors. The method also provides protection against maliciously made calls to a restricted method by caller objects that should not have access to it.

Abstract: The present disclosure describes a unique way for each of multiple processes to operate in parallel using (e.g., reading, modifying, and writing to) the same shared data without causing corruption to the shared data. For example, each of multiple processes utilizes current and past data values associated with a global counter or clock for purposes of determining whether any shared variables used to produce a respective transaction outcome were modified (by another process) when executing a respective transaction. If a respective process detects that shared data used by respective process was modified during a transaction, the process can abort and retry the transaction rather than cause data corruption by storing locally maintained results associated with the transaction to a globally shared data space.

Abstract: A low-level process, which was mapped from a high-level graphical notation diagram, is debugged using the high-level graphical notation diagram. To debug the low-level process, a debugging interface allows a user to set and track breakpoints and other debug events from the high-level graphical notation diagram. When a breakpoint or other debug event is encountered during low-level processing, the high-level graphical notation diagram is updated to show the status of the low-level process.

Abstract: A system and method are provided for inlining a program call between processes executing under separate ISAs (Instruction Set Architectures) within a system virtual machine. The system virtual machine hosts any number of virtual operating system instances, each of which may execute any number of applications. The system virtual machine interprets or dynamically compiles not only application code executing under virtual operating systems, but also the virtual operating systems. For a program call that crosses ISA boundaries, the virtual machine assembles an intermediate representation (IR) graph that spans the boundary. Region nodes corresponding to code on both sides of the call are enhanced with information identifying the virtual ISA of the code. The IR is optimized and used to generate instructions in a native ISA (Instruction Set Architecture) of the virtual machine. Individual instructions are configured and executed (or emulated) to perform as they would within the virtual ISA.

Abstract: XACML (eXtensible Access Control Markup Language) documents, PolicySets and Policies can become long, complex and difficult to completely comprehend. A method is provided for facilitating analysis of such code to make it easier to answer questions such as: Given a particular set of Attribute values (and/or others unknown as of now), what is permitted or denied; are any of the rules redundant; are any of the rules inconsistent; for any pair of policies in the code, what set of Attributes will they both return Permit; how can a policy be refactored into an equivalent set of policies in which each branch of the policy tree pertains to specific values of specified Attributes? To facilitate such analysis and refactoring, every Rule in the collection of policies being analyzed is reduced to an equivalent expression in DNF (Disjunctive Normal Form). Some terms, predicates and other elements may be eliminated.

Abstract: A mounting assembly includes two side rails that mechanically couple to at least two sides on an exterior of a device, where a given side rail includes one or more circumferential edges that define one or more holes on a surface and into an interior of the given side rail, and the surface is approximately parallel to one of the at least two sides on the exterior of the device. Moreover, the mounting assembly includes mechanical collars that mechanically couple to mechanical couplers that mechanically couple the mounting assembly to a chassis in a computer system, where a given mechanical collar is included in a given hole in the given side rail. Additionally, the mounting assembly includes energy-absorbing material encapsulating the mechanical collars, where the energy-absorbing material is positioned between an outer surface of the given mechanical collar and an inner surface of the given hole.

Abstract: One embodiment of the present invention provides a system that determines fan speeds for a set of fans in a computer system. During operation, the system receives time-series data collected by a vibration transducer associated with the computer system, wherein the vibration transducer is configured to record mechanical vibrations from the set of fans. Next, the system performs a spectral analysis on the time-series data to obtain frequency peaks associated with fan speeds for individual fans in the set of fans. The system then identifies fan speeds for the individual fans in the set of fans from the frequency peaks.

Abstract: A hardware unit for parsing an XML document includes embedded logic or circuitry for accessing the document, decoding it to change a character set, validating individual characters of the document, extracting tokens, maintaining a symbol table and generating binary token headers to describe the document's structure and convey the document's data to an application. Tokenization, the process of identifying tokens and generating token headers, may be controlled by a finite state machine that recognizes XML delimiters in the document's markup and activates state transitions based on the current state and the recognized delimiter. The parser unit may be implemented within a hardware XML accelerator that includes a processor, a DMA engine, a cryptographic engine, memory (e.g., for storing a document, maintaining a symbol table) and various interfaces (e.g., network, memory, bus).

Abstract: A reduced-power memory (such as for a cache memory system of a processor or a microprocessor) provides per-sector power/ground control and early address to advantageously reduce power consumption. Selective power control of sectors comprised in the reduced-power memory is responsive to a subset of address bits used to access the memory. The selective power control individually powers-up a selected one of the sectors in response to an access, and then powers-down the selected sector when the access is complete. The power-up is via an increase of differential between power and ground levels from a retention differential to an access differential. Time needed to vary the differential is masked by providing address information used by the selective power control in advance of providing other address information. For example, in a cache, a tag access is overlapped with power-up of a selected sector, thus masking latency of powering up the selected sector.

Abstract: An assembly is disclosed which enables a printed circuit board (PCB) to be added to or removed from a computer system without deactivating other parts of the system. The assembly, which holds the PCB, translates lateral motion into vertical motion to enable lateral motion to be applied to derive the vertical motion needed to plug and unplug a PCB into and out of an expansion slot. This motion translation makes it possible to insert or remove a PCB via a rear, front, or side access portal of a housing rather than through the top of the housing. Thus, the assembly eliminates the need to remove the housing from a rack, or to remove a top from the housing, which in turn eliminates the need to shut down any other parts of the system. Thus, the assembly enables a PCB to be “hot swapped” into and out of a computer system.

Abstract: A management system is provided for the generation of a management object model for performing management of a computer system. The object model includes a structured hierarchy of objects representing components of a computer system. The management system can include component modules operable to define mappings from instrumentation of the components to objects representing those components and configuration modules operable to configure associations between the component modules for the generation of the management object model.

Abstract: A method for sharing dynamically compiled code between different class loaders is provided. In this method, loader-reentrant compiled code is produced from bytecodes by generating native code implementing a class initialization barrier when compiling bytecodes that require a class to be initialized, by generating native code implementing a link resolution barrier when compiling bytecodes that require a symbolic link to be resolved, and by generating code to retrieve loader-dependent data from a loader-dependent table when compiling bytecodes that use data computed from a resolved symbolic link.

Abstract: One embodiment of the present invention provides a system that handles instruction fetch requests that return out-of-order at an IFU of a processor. During operation, the system sends a request to obtain a cache line to an instruction cache, wherein the request can be serviced and the cache line can be sent to a fetch buffer before a preceding cache line for a preceding request has returned from the instruction cache. In response to the request, the system receives the cache line from the instruction cache. Next, the system determines whether the cache line was returned out-of-order with respect to the preceding cache line. If so, the system performs an action to handle the out-of-order return.

Abstract: A data communications system is disclosed. The data communications system comprises two clock domains. Each of the clock domains are coupled to receive a source clock signal. The first clock domain includes a first clock signal and the second clock domain includes a second clock signal, each of the first clock signal and the second clock signal are derived from the source clock signal. The first clock signal has a frequency which is different from that of the second clock signal, and which is not an integer multiple of the frequency of the second clock signal. The first clock domain includes circuitry which is configured to generate both the first clock signal and a reference clock signal derived from the source clock signal.

Abstract: One embodiment of the present invention provides a system that performs load balancing between task queues in a multiprocessor system. During operation, the system conditionally requests load information from a number of neighboring CPUs in a neighborhood of a requesting CPU. In response to the request, the system receives load information from one or more neighboring CPUs. Next, the system conditionally requests one or more neighboring CPUs to transfer tasks to the requesting CPU based on the received load information, thereby balancing load between the CPUs in the neighborhood.