Abstract: A signal duration measurement system compares a known duration, T1, of a test data signal with the duration, T2, of a state of a signal under test. In one embodiment, if T2 compares favorably with T1, then the circuit generating the signal under test ‘passes.’ Otherwise the signal under test ‘fails,’ and a problem has been identified. Furthermore, in one embodiment, T1 can be selectively adjusted to more accurately measure T2. In one embodiment, the test data signal is allowed to travel a signal path, having a known signal propagation delay time, during a single state of the signal under test. The data signal at the beginning of the state, e.g. during the rise of the signal under test, is compared to the data signal captured at the end of the state, e.g. during the fall of the signal under test. If the initial and captured data signals are the same, then the duration of the state of the signal under test is greater than or equal to the signal propagation delay time.

Abstract: An invention is provided for a remote execution system. The remote execution system includes a first application, such as a server application, having a first plurality of virtual service modules, each capable of providing a particular functionality. In addition, a second application, such as a client application, is included that has a second plurality of virtual service modules substantially equivalent to the first plurality of virtual service modules. Each of these virtual service modules is in communication with a substantially equivalent virtual service module of the first plurality of service modules to form a virtual service module set. In this manner, each virtual service module set is capable of interacting with an application as a single software object that is local to the application.

Abstract: A test system includes a device under test and a test circuit board. The device under test includes a plurality of contacts configured to provide output signals. The test circuit board may convey the output signals from the device under test to an analyzer. The test circuit board may include a dielectric layer, a via extending through the dielectric layer, a conductor formed on the dielectric layer and a resistive annular ring having a predetermined resistance value. The resistive annular ring may be formed around the via and may be electrically coupled between the via and the conductor.

Abstract: A noise margin self-diagnostic receiver circuit has been developed. The self-diagnostic circuit includes one comparator for comparing the signal voltage to a high reference voltage, a second comparator for comparing the signal voltage to a low reference voltage, and a logic circuit that activates an alarm if a noise error is detected. The circuit analyzes the data from the comparators and determines if a noise error has occurred dependent on being clocked by one or both of an output from the comparator comparing the signal voltage to the high reference voltage and an output from the comparator comparing the signal voltage to the low reference voltage.

Abstract: An apparatus and method for facilitating development of Java Embedded Server bundles which includes a module containing a set of development tools used in the creation of Java Embedded Server bundles. The module may include a code template tool having sample code segments; a Java Embedded Server manifest generator tool that creates Java Embedded Server manifest files for Java Embedded Server bundles; a Java Embedded Server jar packager tool that packages Java Embedded Server bundles; and a web page link tool having links to Java Embedded Server-related web pages.

Abstract: Role is a comprehensive grouping mechanism. In a client-server directory system, roles transfer some of the complexity to the directory server. A role is defined by its role definition entry. Assigning entries to roles enables applications to locate the roles of an entry, rather than select a group and browse the members list. Additionally, roles allow for support of generated attribute values, and directory server-performed membership verification for clients. By changing a role definition, a user can change an entire organization with ease. Any client with appropriate access privileges can discover, identify and examine any role definition.

Abstract: Disclosed herein is the creation and utilization of automated diagnostic agents that are used by service engineers to diagnose faults, errors and other events or conditions within a grid-based computing system, and provide a derived list of suspect root causes for the events. Related computerized processes and network architectures and systems supporting such agents are also disclosed. The automated diagnostic agents utilize software driven rules engines that operate on facts or data, such as telemetry and event information and data in particular, according to a set of rules. The rules engine utilize a neural network analysis environment to predict in accordance with the rules, facts and data found in the grid-based system to make probabilistic determinations about the grid. Particular memory allocations, diagnostic process and subprocess interactions, and rule constructs are disclosed.

Abstract: Both distortion rate and bit-rate can be considered together when selecting a lowest cost motion estimation signal. A motion estimation signal is generated for each of the candidate motion vectors and candidate mode information vectors for a macroblock. An estimated amount of encoding bits is determined for each of the candidate motion vectors, candidate mode information vectors, and quantized coefficients. A bit-rate is computed based on the estimated amount of encoding bits. In addition, a current macroblock is reconstructed with each of the candidate vectors, and distortion measured between each of the reconstructions and the current macroblock. A sum is computed for each distortion measurement and corresponding bit-rate. The lowest sum represents the lowest cost motion estimation signal.

Abstract: In some embodiments, an electronics assembly may include a frame with a motherboard and a plurality of daughterboards. The frame may have an opening opposite the motherboard to allow insertion of the daughterboards into the frame or removal of the daughterboards from the frame. An injector/ejector mechanism for each daughterboard may be located on the daughterboard or the frame. The frame may further include a flange that extends along the frame at or adjacent to the opening and on which the injector/ejector mechanism of each daughterboard is attached or engages at different locations along the length thereof. The flange may be divided into separate sections that correspond to the different locations to allow the flange to flex at any location along the frame during insertion of a daughterboard without the flexing affecting the position of any adjacent location of the flange with respect to the motherboard.

Abstract: A system for on-chip testing of embedded memories using Address Space Identifier (ASI) bus in Scalable Processor ARChitecture (SPARC) microprocessors. An integrated circuit includes a plurality of memory arrays, Address Space Identifier (ASI) bus interface logic connected by an ASI bus to the plurality of memory arrays, and a memory control unit and a memory built-in self-test (MBIST) engine connected to the ASI bus interface logic. Rather than direct access, the MBIST engine utilizes the ASI bus interface logic and the ASI bus to perform memory testing. The MBIST engine, programmed with memory array parameters, includes a programmable state machine controller to which is connected a programmable data generator, a programmable address generator, and a programmable comparator. The data generator provides data as appropriate. The address generator provides addresses as appropriate. The comparator provides test results information for the particular test situation.

Abstract: In response to programmer input of a trigger token, a program editor creates a pair of boundary tokens encapsulating an embedded lexical context and positions an insertion point within the embedded lexical context. The operations on the embedded lexical context are preferably performed using an embeddable sub-editor specialized to the task at hand. Since boundary tokens are generated in pairs, stability of lexical boundaries is enforced. Accordingly, stable implementations of certain desirable behaviors, including language-oriented advanced program typography that is robust to user edits, are facilitated using the invented techniques.

Abstract: A system and method of predicting network data traffic includes coupling a first group of clients to a current server that results in a current CPU utilization of the current server. A second group of clients are coupled to the current server. A load multiple is determined and the current CPU utilization is compared to a predicted CPU utilization. A server requirement is increased if the current CPU utilization is greater than or equal to the predicted CPU utilization.

Abstract: One embodiment of the present invention provides a system that dynamically allocates physical registers in a windowed processor architecture. The system includes a physical register file and a register map that maps architectural registers defined within an executing program to physical registers within the physical register file. The system also includes a window allocation mechanism that allocates a new name space for a register window without allocating physical registers for the register window, thereby allowing the physical registers to be dynamically allocated as needed instead of being allocated at window initialization time.

Abstract: A method of determining at least one ratio of transistor sizes. The method includes creating a sizing model by replacing at least one logic element in a circuit description with a sizing element that includes a piece-wise-linear current source. The method also includes determining a steady state solution to the sizing mode and determining at least one ratio of transistor sizes from the steady state solution. The method may also include determining at least one dimension of a transistor based at least in part upon the ratio of transistor sizes.

Abstract: A system and method for providing secure exchange of messages between peers in peer groups. Embodiments may be used to provide secured sessions between peers in the peer-to-peer network. Embodiments may also be used to provide secured group sessions among a plurality of peers. A first peer may generate and send a public key to a second peer. The second peer may generate a session key from the public key. The second peer may send the session key to the first peer, or alternatively to two or more peers in a group session. The session key may be secured when sending. Messages and/or other data exchanged between the two peers may be encrypted and decrypted using the session key.

Abstract: A metadata tree structure having a plurality of nodes (slabs), each node containing a MD table. Each of the MD tables has a plurality of entries. Each of the entries in the MD tables represents a contiguous range of block addresses and contains a pointer to a cache slot storing a date block corresponding to the block address, or an indicator to indicate that the corresponding data block is not stored in a NVRAM cache slot. Each MD table also contains a block address range indicator to indicate the contiguous range of block addresses, and at least one pointer to point to any parent or child nodes. In an alternative embodiment, the pointer of each MD entry may point to a disk address if the data is not in cache. For such an embodiment, portions of the MD store may be stored to disk.

Abstract: One embodiment of the present invention provides a system that fixes bit errors encountered during references to a cache memory. During execution of an application, the system performs a reference to the cache memory by retrieving a data item and an associated error-correcting code from the cache memory. Next, the system computes an error-correcting code from the retrieved data item and compares the computed error-correcting code with the associated error-correcting code. If the computed error-correcting code does not match the associated error-correcting code a bit error has occurred. In this case, the system stores an identifier for the reference in a register within a set of one or more registers associated with the cache memory, so that the bit error can be fixed at a later time. The system also allows the application to continue executing.

Abstract: A system and method for facilitating delivery of instructions for operating a controller (e.g., an FPGA—Field Programmable Gate Array) of a hardware device (e.g., a network interface circuit) of a computer system. A device driver for the hardware device comprises traditional device driver functionality (e.g., for managing operation of the device at a layer above the physical layer), plus a set of instructions for operating the controller. During attachment of the device driver to the hardware device, or during subsequent hardware initialization of the device, the set of instructions for operating the controller is downloaded to the controller from the device driver.

Abstract: A system for emulating a telematics client is provided. The system includes a workstation in communication with a display screen. A software stack configured to be executed by the workstation to implement functionality for a telematics client is included. The software stack imitates a configuration of an in-vehicle telematics stack of a telematics control unit (TCU). The software stack includes a service gateway for loading an emulator. A user interface (UI) manager configured to communicate with the loaded emulator is included with the software stack. The UI manager enables a presentation of TCU user interface without accessing the TCU. Methods to emulate a user interface and loading an emulator on a workstation are also provided.

Abstract: One embodiment of the present invention provides a system that corrects bit errors in temporary results within a central processing unit (CPU). During operation, the system receives a temporary result during execution of an in-flight instruction. Next, the system generates a parity bit for the temporary result, and stores the temporary result and the parity bit in a temporary register within the CPU. Before the temporary result is committed to the architectural state of the CPU, the system checks the temporary result and the parity bit to detect a bit error. If a bit error is detected, the system performs a micro-trap operation to re-execute the instruction that generated the temporary result, thereby regenerating the temporary result. Otherwise, if a bit error is not detected, the system commits the temporary result to the architectural state of the CPU.