Abstract: Improved techniques for reducing the time and cost associated with producing compiler products are disclosed. A programming system including an enhanced compiler suitable for compilation of source programs is disclosed. The enhanced compiler can be used to compile source programs so that template (or generic) instances already available from the libraries are not recreated. The enhanced compiler can efficiently compile a request to create an instance by determining whether the instance is already available in one of the libraries. If the instance is already available from one of the libraries, the instance need not be created. In comparison with conventional models, the enhanced compiler can access libraries directly without requiring a significant amount of preparatory work and/or costly operations such as preparation of options files and transformation of instance names to linker symbol names. As a result, the enhanced compiler is more efficient (faster) than convention compilers.

Abstract: A system and method for reducing shared memory write overhead in multiprocessor system. In one embodiment, a multiprocessing system implements a method comprising storing an indication of obtained store permission corresponding to a particular address in a store buffer. The indication may be, for example, the address of a cache line for which a write permission has been obtained. Obtaining the write permission may include locking and modifying an MTAG or other coherence state entry. The method further comprises determining whether the indication of obtained store permission corresponds to an address of a write operation to be performed. In response to the indication corresponding to the address of the write operation to be performed, the write operation is performed without invoking corresponding global coherence operations.

Abstract: A processor includes a tagging buffer for storing information that advises the processor of potential memory collisions caused by program instruction pairs that refer to the same memory address. In one method for avoiding memory collisions, a program having tagging code identifying program instruction pairs of the program that refer to a same memory address is compiled. The program instruction pairs in the compiled program code are processed while verifying an order in which the program instruction pairs are to be executed using the compiled tagging code, which is loaded into a tagging buffer. In another method, a program that does not include tagging code is compiled. When a trap occurs in the processing of a program instruction pair, program counters that cause the instructions to be executed in a desired order are added to a tagging buffer. A computer system including the processor also is described.

Abstract: According to the invention, a processing core (12) comprising a processing pipeline (100) having N-number of processing paths (56), each of which process instructions (54) on M-bit data words. In addition, the processing core (12) includes one or more register files (60), each preferably having Q-number of registers which are M-bits wide. Preferably, one of the Q-number of registers in at least one of the register files (60) is a program counter register dedicated to hold a program counter, and one of the Q-number of registers in at least one of the register files is a zero register dedicated to hold a zero value. In this manner, program jumps can be executed by adding values to the program counter in the program counter register, and memory address values can be calculated by adding values to the program counter stored in the program counter register or to the zero value stored in the zero register.

Abstract: A Compact Peripheral Component Interconnect (CPCI) system includes a circuit board with a front card (e.g., motherboard) coupled to a power supply via the circuit board. The CPCI system is adapted to provide for the dynamic control and change of power sequences during the front card's lifetime. That is, as power sequencing requirements evolve, change or deviate from what was the standard, the present extended front card can automatically evolve, change or deviate from what was the standard. The front card may also control and change power sequences without requiring modification to be made to the hardware of the front card.

Abstract: A system and method for interaction and access to shared content among clients and services in a distributed computing environment. A client may access a space service. The space service may store one or more XML service advertisements and/or other XML content in a space, and each of the service advertisements may include information which is usable to access and execute a corresponding service. The space service may include an XML schema which specifies one or more messages usable to invoke functions of the space service. For example, the schema may specify methods for reading advertisements from the space and publishing advertisements in the space. In accessing the space service, the client may send information such as an XML message (as specified in the schema) to the space service at an Internet address. In accessing the space service, the client may search the one or more service advertisements stored in the space. The client may select one of the service advertisements from the space.

Abstract: A graphics system comprises pixel calculation units and a sample buffer which stores a two-dimensional field of samples. Each pixel calculation unit selects positions in the two-dimensional field at which pixel values (e.g. red, green, blue) are computed. The pixel computation positions are selected to compensate for image distortions introduced by a display device and/or display surface. Non-uniformities in a viewer's perceived intensity distribution from a display surface (e.g. hot spots, overlap brightness) are corrected by appropriately scaling pixel values prior to transmission to display devices. Two or more sets of pixel calculation units driving two or more display devices adjust their respective pixel computation centers to align the edges of two or more displayed images. Physical barriers prevent light spillage at the interface between any two of the display images. Separate pixel computation positions may be used for distinct colors to compensate for color distortions.

Abstract: A method, system and protocol suitable for mediating communication between an application written in a platform independent language, running on a specific processor or computing platform, and an application written in the processor's native language. As part of the present invention, an application written in a platform independent code may be compiled and/or linked to a first mediation module and an application written in the processor's native code may be compiled and/or linked to a second mediation module. The first and second mediation modules may communicate with each other utilizing a stream protocol providing for communication of various data types, including but not limited to function calls, function parameters, function results, and event notification.

Abstract: A system and method for database design is disclosed. DDL code, which may be generated by a suitable CASE tool, is bound to tags rather than to specific system parameters. The DDL code may be stored in a suitable data structure, such as a directory tree. A series of scripts are provided with the DDL code. The scripts may invoke an editor, such as the Unix stream editor, to bind the tagged DDL code to specific system parameters.

Abstract: A software package verification tool enables verifying a software package that includes at least one software component. The tool includes at least one test module defining a test of at least one parameter of a software component of the package. It also includes a control module operable to access a framework that identifies each test module and to cause at least one test module to perform the test defined thereby for verifying the package. The framework, within which individual test modules may be added or deleted as required, provides a flexible test structure for software packages. Typically, the framework identifies a plurality of test modules for verifying the correctness of a particular software package. In such a case, the framework can identify a priority for each test module for effecting an ordering of the tests. This enables the performance of the tests to be efficient, avoiding, for example, unnecessary tests that are redundant if the software package fails a more fundamental test.

Abstract: Computer-readable medium provided with a memory area (2; 26, 28) for storing data and a distinct microprocessor (3) having a communication interface (4), a memory unit (7) and a processor unit (5) connected to both the communication interface (4) and the memory unit (7). The data may include a first data portion which is arranged to be read and decrypted by a computer arrangement (11) provided at least one condition is met, and the microprocessor (3) being arranged to generate at least one cryptographic key once the condition is met that is necessary to decrypt the data. The invention is also directed to a computer arrangement arranged to communicate with such a medium.

Abstract: A technique for flattening architectural register windows into flattened space depending on a current window pointer to a register window is provided. The technique involves converting an n-bit value of a particular register in a register window to an x-bit value dependent on the current window pointer, where x is greater than n, and where the x-bit value is used for register dependency checking among a plurality of instructions.

Abstract: A program interpreter for computer programs written in a bytecode language, which uses a restricted set of data type specific bytecodes. The interpreter, prior to executing any bytecode program, executes a bytecode program verifier procedure that verifies the integrity of a specified program by identifying any bytecode instruction that would process data of the wrong type for such a bytecode and any bytecode instruction sequences in the specified program that would cause underflow or overflow of the operand stack. If the program verifier finds any instructions that violate predefined stack usage and data type usage restrictions, execution of the program by the interpreter is prevented. After pre-processing of the program by the verifier, if no program faults were found, the interpreter executes the program without performing operand stack overflow and underflow checks and without performing data type checks on operands stored in operand stack. As a result, program execution speed is greatly improved.

Abstract: Systems and methods for routing messages in an interconnection fabric are provided. The fabric includes a plurality of nodes, each node having, for example, four ports coupled to adjacent nodes in the fabric. A source node initiating a message in the fabric can transmit the message out of one of its four ports. Between a source node and a destination node, there are at least four independent paths which may be taken, depending on the output port from the source node. However, the precise path is not expressly delineated in the message. Instead, the message contains the address of the destination node, the address of the originating node, and a target region for the message. Each intermediate node is configured to receive a message via one of its four ports, and then select an appropriate output port based on the location of the port which received the message combined with the address and target information contained in the message.

Abstract: A system and method for assessing binary compatibility between software modules permits software developers to register with a system, download software tools for testing binary compatibility between their software products and one or more ABIs. The system further enables software developers to certify their binary compatibility with one or more ABIs by uploading compatibility information to the system. A unique identifier of the software, e.g., the MD5 signature of the binary code, may be uploaded with the results of the compatibility test. The results of the compatibility test and the unique identifier may be stored in a database to record whether the developer's software is binary compatible with one or more of the ABIs. In addition, computer users may register with the system, utilize a tool that collects the MD5 signatures of the binary files on their computer(s) and forward the MD5 signatures to the system.

Abstract: Improved techniques for reducing the size of compiler products are disclosed. The techniques facilitate reduction of size by providing differential schemes aimed at producing compiler related information in a compressed form. The compressed compiler related information include symbol names associated with symbols encountered in programming languages. The improved techniques yield improved compilation times and compiler products that utilize substantially less storage space (e.g., disk storage space).

Abstract: A heatsink for a memory module includes a substantially planar contact portion for forming a thermal contact with the memory module and for mounting the heatsink on the memory module. One or more formations for emitting heat are also provided, the formations for emitting heat being in thermal communication with the contact portions.

Abstract: An improved mechanism is provided for generating an execution log and coverage data for a set of computer code. To minimize the amount of storage required for storing execution log information, the mechanism: (1) stores only information pertaining to instructions that are actually executed during execution; and (2) stores the information in a hierarchically organized set of lists. In addition, to minimize the impact of execution log and coverage data generation on the execution of the computer code, coverage data is generated after execution has completed. By generating the execution log and coverage data in this manner, storage requirements are reduced, and execution performance is improved.

Abstract: A system and method for correcting data errors. A system for correcting errors in blocks of data received over a communication medium includes an error history unit coupled to an error correction unit. The error history unit may maintain information associated with each bit position of the blocks of data in which a correctable error has occurred. The error correction unit may perform an error correction on a given block of data using an error correction code capable of correcting at least a single bit error and detecting multiple bit errors. Further, in response to detecting a multiple bit error, the error correction unit may correct subsequent errors in the given block of data dependent upon the information maintained by the error history unit.

Abstract: A server blade is provided which comprises a processor. The server blade additionally comprises an enclosure which encloses the processor. The server blade is configured as a field replaceable unit removably receivable in a carrier of a modular computer system, and is configured as an oversized unit to span more than one standard information processing module receiving location in the carrier.