Abstract: Embodiments consistent with the principles of the present invention provide improved results, compared to IEEE Std. 754, for floating point operations used in interval arithmetic calculations. One embodiment consistent with the principles of the present invention provides a method of enhancing support of an interval computation when performing a floating point arithmetic operation, comprising the steps, performed by a processor, of receiving a first floating point operand, receiving a second floating point operand, executing the floating point arithmetic operation on the first floating point operand and the second floating point operand, determining whether a NaN substitution is necessary, producing a floating point result if the NaN substitution is determined to be unnecessary, and substituting an alternative value as the floating point result if the NaN substitution is determined to be necessary.

Abstract: One embodiment of the present invention provides a technique for assembling semiconductor chips. First, multiple semiconductor chips are permanently laminated together into a plurality of laminated chip assemblies, wherein the semiconductor chips within the laminated chip assembly communicate with each other through electrically conductive connections. Next, laminated chip assemblies are stacked together to form a stack of semiconductor chips without permanently bonding the laminated chip assemblies together, wherein the laminated chip assemblies communicate with each other using capacitive coupling.

Abstract: A method and apparatus for adjusting clock skew involves using a plurality of oscillators distributed across the apparatus where at least one of the plurality of oscillators has a frequency dependent on a characteristic of the apparatus. A processor is arranged to adjust a bias generator dependent on the frequency. The bias generator is arranged to adjust a delay through a tunable buffer. The tunable buffer is arranged to propagate a clock signal dependent on the adjustment of the delay through the tunable buffer dependent on the bias generator.

Abstract: Embodiments of the present invention relate to the implementation of an Application Programming Interface (API) that enables platform independent plug-ins to work with browser applications. In one or more embodiments of the present invention, the API allows platform independent plug-ins to use XPCOM (Cross Platform Component Object Model), a technology that allows software components of different various programming languages to communicate. In one or more embodiments of the present invention, the API enables platform independent plug-ins to take advantage of existing BlackConnect and Scriptable Plug-In API technologies to integrate with the native plug-in API. Embodiments of the present invention ensures backward code compatibility by allowing the current platform independent plug-in API and browser API to remain unchanged. Furthermore, embodiments of the present invention enables platform independent plug-ins to communicate and use components created in native programming languages such as C++.

Abstract: An apparatus and method for scheduling execution of multiple threads on a shared processor resource is described in connection with a multithreaded multiprocessor chip. Using a thread selection policy that switches between available threads every cycle to give priority to the least recently executed or scheduled threads, different threads are able to operate in a way that ensures no deadlocks or livelocks while maximizing aggregate performance and fairness between threads. Prioritization is accomplished by monitoring and sorting thread status information for each thread, including speculative states in which a thread may be speculatively scheduled, thereby improving usage of the execution pipeline by switching a thread in with a lower priority.

Abstract: A multi-thread processor including a processing core. The processing core including multiple threads and a scheduler. The scheduler includes a thread state register. The thread state register being capable of storing a selective wait state for a selected one of the threads. A method of scheduling threads in a multi-thread processor is also disclosed.

Abstract: A processor chip is provided. The processor chip includes a plurality of processing cores where each of the processing cores being multi-threaded. The plurality of processing cores are located in a center region of the processor chip. A plurality of cache bank memories are included. A crossbar enabling communication between the plurality of processing cores and the plurality of cache bank memories is provided. The crossbar includes a centrally located arbiter configured to sort multiple requests received from the plurality of processing cores and the crossbar is defined over the plurality of processing cores. In another embodiment, the processor chip is oriented so that the cache bank memories are defined in the center region. A server is also included.

Abstract: A method generates and verifies a design-for-test (DFT) library for an automatic test pattern generator (ATPG) tool. The method includes (a) creating a synthesis library including primitives to be used to create the modules, the primitives being the same as primitives used by the ATPG tool, (b) creating a register transfer level (RTL) description for each module, (c) performing synthesis using the synthesis library and the RTL description to create a gate level description for each module, and (d) generating the DFT library by converting a hardware description language (HDL) of the gate level description into a script language for the ATPG tool to create a DFT file for each module. The method may further include (e) converting the DFT files into a RTL description to create a pseudo-RTL description for each module, and (f) comparing the RTL description and the pseudo-RTL description for verification of the DFT library.

Abstract: A server blade is provided with an enclosure. The server blade can be provided with a plurality of processors in the enclosure. The server blade can be configured as a field replaceable unit removably receivable in a carrier of a modular computer system, for example a high density blade server system. The enclosure for such a multiprocessor server blade can be larger that a standard enclosure for a single processor server blade. The carrier can be configured to receive such an oversized server blade enclosure as well as a standard enclosure.

Abstract: One embodiment of the present invention provides a circuit that preferentially grants requests. This circuit monitors at least two inputs for request signals and at least two inputs for enable signals, wherein each request signal is associated with a corresponding enable signal. If any enable signal is asserted and only one request signal is asserted, the circuit asserts a grant signal associated with the asserted request signal. Otherwise, if a single enable signal is asserted and multiple request signals are asserted, the circuit preferentially asserts the grant signal of the request signal associated with the asserted enable signal.

Abstract: In one embodiment, a memory controller is coupled to a memory subsystem and controls accesses to the memory subsystem. In addition, a temperature sensor is positioned to detect a temperature associated with the memory subsystem. In this embodiment, the memory controller is configured to selectively insert one or more idle clock cycles between a first memory access and a second memory access depending upon the sensed temperature. In a further embodiment, a sensor is positioned to detect a power condition associated with the memory subsystem. In this embodiment, the memory controller is configured to selectively insert one or more idle clock cycles between a first memory access and a second memory access depending upon the detected power condition.

Abstract: A computer system coupled with a pipelined network includes a plurality of initiator nodes coupled to send packets into the network. A plurality of target nodes receive packets sent into the network. The network uses a plurality of pipeline stages to transmit data across the network. Each pipeline stage consumes a known time period, which provides for a predetermined time period for transmission for each packet that is successfully sent from one of the initiator nodes to one of the target nodes. The pipelined network is synchronous in that boundaries of all the pipeline stages are aligned. The pipeline stages include at least an arbitration stage to obtain a path through the network, a transfer stage during which a data packet is transmitted, and an acknowledge stage during which successful transmission of a packet is indicated by the target. To simplify network design, all the pipeline stages are implemented to have equal length.

Abstract: The invention describes a method an apparatus to minimize the costs introduced in the native code of a method M in order to make it executable (concurrently or serially) by multiple tasks, wherein M's native code is produced by the dynamic compiler of a multitasking virtual machine. One embodiment of the present invention describes a mechanism that annotates the shared runtime representation of classes with information that identifies the particular event that triggered the initialization of these classes, and in particular, if that event is the execution of class initialization barrier from a method of another class. These annotations are then used during each dynamic compilation of a method M of a class C to determine when native code corresponding to a class initialization barrier needs to be generated in the task re-entrant native code produced by the dynamic compiler for M.

Abstract: A technique for handling a condition code modifying instruction in an out-of-order multi-stranded processor involves providing a condition code architectural register file for each strand, providing a condition code working register file, and assigning condition code architectural register file identification information (CARF_ID) and condition code working register file identification information (CWRF_ID) to the condition code modifying instruction. CARF_ID is used to index a location in a condition code rename table to which the CWRF_ID is stored. Thereafter, upon an exception-free execution of the condition code modifying instruction, a result of the execution is copied from the condition code working register file to the condition code architectural register file dependent on CARF_ID, CWRF_ID, register type information, and strand identification information.

Abstract: A system and method for providing resources to networked devices for participating in a peer-to-peer environment. In one embodiment, a peer computing system on a network may include one or more bootstrap nodes that may provide, to devices coupled to the network, mechanisms for accessing resources for participating in the peer-to-peer environment. The bootstrap nodes may be peer nodes. The resources may give the devices access to services each of which may implement peer-to-peer platform protocols. The devices may be pre-configured to access one or more predefined peer nodes for information on bootstrap nodes. Alternatively, devices may use a bootstrapping mechanism to locate bootstrap nodes on the network.

Abstract: Disclosed are novel methods and apparatus for manipulating and generating a real-time counter in network computing environments. In an embodiment, a method of tracking a defect is disclosed. The method includes providing a defect abstract, the defect abstract including information to identify the defect; identifying a component having the defect; assigning a user to resolve the defect; and assigning a defect number to identify the defect, the defect number obtained by incrementing a counter value stored in a file, the file being accessible by a single user at a time.

Abstract: Embodiments of a system and method for hierarchically organizing rules and for evaluating and executing the hierarchy of rules. Each rule in the hierarchy of rules may include a precondition and an action to be executed if the precondition is met. When evaluating and executing the rules, if a precondition of a rule in the hierarchy is not met, then the action of the rule is not executed. Further, rules that descend from the rule in the hierarchy of rules are precluded from evaluation and execution. In one embodiment, modification of the hierarchy of rules may be performed without modification to an application using the hierarchy of rules.

Abstract: Various embodiments of message gate pairs are described. A message gate pair may provide a mechanism for communicating requests from clients to services and response from services to clients. A message gate pair may be used to create a secure atomic bi-directional message channel for request-response message passing. The distributed computing environment may employ a message transport in which a message gate exists on both the client and the service. The two gates may work together to provide a secure and reliable message channel. Client and service gates may perform the actual sending and receiving of the messages from the client to the service using a protocol specified in a service advertisement. The message gates may provide a level of abstraction between a client and a service. A client may reference a service through a message gate instead of referencing the service directly.

Abstract: An enhanced Java Bytecode verifier suitable for operation in a Java computing environment is disclosed. The enhanced Java Bytecode verifier operates to determine whether one or more Java conventional Bytecode commands within a stream of Bytecodes are likely to place a reference to a Java object on the execution stack. In one embodiment, the conventional Java Bytecode commands identified as such are translated by the enhanced Java Bytecode verifier into one or more corresponding Java commands. When a corresponding command is executed, the reference associated with the conventional Java command is placed on a reference stack as well as the execution stack.

Abstract: Virtual registers are mapped to architectural or physical registers according to a register map that is configurable with software. In one embodiment, only privileged software can configure the register map. In another embodiment, a portion of the register map is configurable with non-privileged software, and another portion is only configurable with privileged software. In yet another embodiment the register map is fully configurable by user software. The configurable register map provides backwards compatibility to code written for hardware-defined register mapping, while allowing flexible approaches to register mapping in code generated for a processor architecture using a software controllable register map.