Abstract: A carry look-ahead adder capable of adding or subtracting two input signals includes first stage logic having a plurality of carry-create and carry-transmit logic circuits each coupled to receive one or more bits of each input signal. Each carry-create circuit generates a novel carry-create signal in response to corresponding first bit-pairings of the input signals, and each carry-transmit circuit generates a novel carry-transmit signal in response to corresponding second bit-pairings of the input signals. The carry-create and carry-transmit signals are combined in carry look-ahead logic to generate accumulated carry-create signals, which are then used to select final sum bits.

Abstract: One embodiment of the present invention provides a system that facilitates determining whether a disk drive is likely to fail. The system monitors a first acoustic signal emitted from the disk drive during operation of the disk drive. Next, the system compares characteristics of the first acoustic signal against characteristics of a first baseline acoustic signal that reflects normal operation of the disk drive. If the first acoustic signal differs by a predetermined amount from the first baseline acoustic signal, the system indicates that the disk drive is likely to fail.

Abstract: A cooling system is presented. The system includes a cooling circuit and at least one electronic component coupled to a surface. One or more heat dissipation structures are in thermal contact with the at least one electronic component. At least one sliding seal mechanism is coupled to the cooling circuit and the one or more heat dissipation structures so as to provide fluid communication between the cooling circuit and the one or more heat dissipation structures. The cooling circuit may include a tank that has a volumetric center and that is capable of holding a maximum volume of fluid. Fluid enters the tank through a tank input and exits the tank through a tank output. The tank output has a port through which fluid from the tank enters the tank output. The tank is capable of being filled with a fluid volume that is less than the maximum volume of fluid, such that the port remains immersed in fluid irrespective of tank orientation.

Abstract: One embodiment of the present invention provides a system that performs modular division. This system contains a number of registers, including: a register A that is initialized with a value X; a register U that is initialized with a value Y; a register B that is initialized with a value M; and a register V that is initialized with a value 0. The system also includes a temporary register H, and a temporary register L. An updating mechanism is configured to iteratively reduce the contents of registers A and B to a value of one by applying a plurality of operations to registers A, B, U and V. During operation, this updating mechanism temporarily stores A+B in the temporary register H, and temporarily stores U+V in the temporary register L.

Abstract: A microprocessor includes multiple register files. In a single thread mode, the microprocessor allows a single thread to have access to multiple ones of the register files. In a multi-thread mode, each thread has access to respective ones of the register files. In the multi-thread mode, multiple threads are simultaneously executing. Circuitry and hardware are provided to facilitate the respective modes and to facilitate transitions between the modes.

Abstract: A computer system comprises a host processor, and a service processor for providing system management functions within the computer system. One or more external communication devices are provided, for example ethernet ports. The external communication devices include at least one management communication device that communicates with the service processor. The management communication device is controlled by a signal from the service processor and is operative to send and receive data only when it receives the signal from the service processor.

Abstract: The present application describes various embodiments of a method and an apparatus for determining electromigration risks for signal nets in integrated circuits. A model for each one of the global nets connecting various circuit blocks in an integrated circuit is created using circuit blocks' timing model and detailed standard parasitic format representation (DSPF) of each global net. The final layout of the integrated circuit is not necessary to determine the electromigration risks. The models can be generated during the early stages of the design cycle once the DSPF of the global nets is available.

Abstract: An integrated circuit that uses a functional unit that outputs one set of values when in a power saving mode is provided. The functional unit, generally pipelined, is capable of being in the power saving mode dependent on an instruction decode/issue unit, and when in the power saving mode, the functional unit, using power saving mode circuitry, outputs one set of values as seen by components external to the functional unit regardless of the state the functional unit is in when the functional unit is initially put in the power saving mode.

Abstract: A system and method of determining an in-situ signal path delay on an integrated circuit. The system and method includes inputting a first signal to a first input node of a first signal path and inputting a second signal to a second input node of a reference signal path. A phase of the first signal output from a first output node of the first signal path is compared to a phase of the second signal output from a second output node of the reference signal path. A phase error signal is output.

Abstract: A system and method for providing pluggable authentication and access control in computer systems and services are described. The authentication and access control process may be categorized into three components: an authentication protocol, a user repository and an access control model. In one embodiment, the authentication and access control mechanism may be implemented as three pluggable modules: an authentication protocol handler module for the authenticator side, an authentication protocol handler for the side to be authenticated, and an access control context module on the authenticator side. The pluggable modules may be exchangeable to support a variety of authentication types, user repositories, and access control models. The authentication protocol handlers provide symmetrical methods to handle requests and responses in the authentication process that reflect the symmetrical nature of the authentication process.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention time profile program threads using data corresponding to states of the registers of a processor(s) executing the threads. Methods, systems, and articles of manufacture consistent with the present invention determine whether a selected thread of execution of a multi-threaded program is running by suspending execution of the multi-threaded program, retrieving register data corresponding to the selected thread, computing register information based on the register data, comparing the computed register information with stored register information from a previous suspension of the multi-threaded program, and regarding the selected thread as running if the computed register information is different from stored register information.

Abstract: Provided is a method and an apparatus to verify an extensible Markup Language (XML) document against a compiled Document Type Definition (DTD). A DTD document can specify valid elements and the sequence of the valid elements in the XML document. During compilation, the elements of the DTD document are added to a structure, such as a tree. Consequently, nodes in the tree can contain elements, which are verified against the elements in the XML document. If there is a match between all the elements in the XML document and elements of the structure, then the XML document is valid. A valid XML document is thus verified and can be processed. Otherwise, an error can result, indicating an invalid XML document.

Abstract: A structure includes a substrate, first and second signal lines above the substrate, where unused substrate surface area exists between the first and second signal lines, and a first shield line in the unused substrate surface area. To define the first shield line, the signal line layout which includes the first and second signal lines is defined. Any areas which are not signal lines are then defined as unused areas of the substrate. The shield lines including the first shield line are then defined in portions of the unused areas of the substrate. In this manner, shield lines are automatically designed at every available location without requiring any allocation of substrate surface area.

Abstract: A method, apparatus and computer program product for a non-atomic (i.e., user controllable) format converter that affords a user the ability to control the structure of the converted document as well as selectively add information to or otherwise modify selected portions of the converted document is described.

Abstract: A support module monitors the operation of at least one information processing module domain by automatically applying at least one test at intervals to an information processing module domain to be monitored and reporting a fault when the test is unsuccessful. On initiation of an information processing module domain, the support module automatically applies a set of tests to the information processing module domain, and, where a test provides a positive result, reapplies the test at intervals to monitor the operation of the information processing module domain.

Abstract: Methods and systems consistent with the present invention allocate memory for program data during fast Fourier transform computation in a way that is favorable for a given access pattern for the program data, and for the memory architecture of a given data processing system. As a result, the overhead associated with accessing the program data is reduced compared to typical memory allocation performed during fast Fourier transform computation. Thus, a fast Fourier transform computing program that manipulates the program data typically runs faster and produces results more quickly.

Abstract: A method and apparatus is provided by which a die designer can efficiently evaluate package routings associated with a die connection bump layout of a die. The die designer is equipped to determine appropriate placement of die connection bumps around a periphery of the die, designate signal and power assignments for die connection bumps, and check routings between die connection bumps and associated package pins. The die designer can efficiently iterate, without recourse to a package designer, through numerous die connection bump placement and assignment configurations to develop a die connection bump layout that is routable within a package. Thus, time required for iteration between the die designer and the package designer to establish a proper placement and assignment of die connection bumps is substantially reduced. Also, as design variables and constraints change during a die design process, the die designer can efficiently re-evaluate a die-to-package interface without recourse to the package designer.

Abstract: A method is provided, the method comprising collecting related signals capable of having unrelated names into a Krutibus, defining a bus capable of connecting the related signals in a bus definition file in the Krutibus and providing at least one of component declarations of the bus and different uses of the bus in a hardware description language (HDL) circuit description using the bus definition file in the Krutibus. The method also comprises providing a Krutibus preprocessor to read the hardware description language (HDL) circuit description for the at least one of the component declarations of the bus and the different uses of the bus and to generate a hardware description language (HDL) circuit description naming the bus components.

Abstract: Methods and components in an interconnect system for improving the performance of the system with respect to increasing bandwidth in a serial link, increasing the processing speed of a packet in a node, and improving the calibration of links in the system are described. In one aspect of the present invention, a method of encoding framing data in a packet such that less than the normal number of framing bits is required. For example, a flit, the data unit sent over a serial link in one clock cycle, can be 88 bits in length, and a packet can be made up of one, two, or four flits. If the packet is a one- flit packet, two framing bits are inserted into the packet. If the packet is two flits, four framing bits are inserted into the packet, and if it is a four-flit packet, eight framing bits are inserted.

Abstract: A computer system may include a host computer system and a storage device such as a tape device that includes one or more tape drives. The host computer system may be configured to provide commands to the storage device and to initiate a timeout period for each command provided to the storage device. The host computer system may be configured to initiate a first timeout period if a first type of command is provided to the storage device, to initiate a second timeout period if a second type of command is provided to the storage device, and to initiate a third timeout period if a third type of command is provided to the storage device, where the first timeout period, the second timeout period, and the third timeout period each have a different duration.