Abstract: A processor is provided. The processor includes at least two cores. The at least two cores have a first level cache memory and are multi-threaded. A crossbar is included. A plurality of cache bank memories in communication with the at least two cores through the crossbar is provided. Each of the plurality of cache bank memories communicates with a main memory interface. A plurality of input/output interface modules in communication with the main memory interface and providing a link to the at least two cores are included. The link bypasses the plurality of cache bank memories and the crossbar. Threading hardware configured to enable the at least two cores to switch from a first thread to a second thread in a manner hiding delays caused by cache accesses is included. A server and a method for determining when to switch threads in a multi-core multi-thread environment are included.

Abstract: A server including an application processor chip. The application processor chip includes a plurality of processing cores, where each of the processing cores are multi-threaded. A plurality of cache bank memories is included. Each of the cache bank memories include a tag array region configured to store data associated with each line of the cache bank memories, a data array region configured to store the data of the cache bank memories, an access pipeline configured to handle accesses from the plurality of processing cores, and a miss handling control unit configured to control the sequencing of cache-line transfers between a corresponding cache bank memory and a main memory. A crossbar enabling communication between the plurality of processing cores and the plurality of cache bank memories is provided.

Abstract: Clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention do not include complementary logic elements. According to the invention, the complementary logic function of the prior art is replaced by a single transistor appropriately sized to provide the complementary output. In addition, the clocked half-rail differential logic circuits are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock. The addition of the sense amplifier circuit, and second delayed clock signal, allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic block to provide a driver function.

Abstract: A computer method for automatically troubleshooting and preventing problems on a computer system. The method includes receiving data corresponding to the computer system including core files, supplemental configuration information, and other data. The method continues with processing the computer system data into a format useful for rapid analysis. The method uses a knowledge repository of phases and scripts. Each phase is a logical organization of scripts. Each script is an executable for identifying both the conditions that can lead to a problem as well as determining an actual instance of a problem. Execution of the method includes execution of the phases contained in the repository. Several optimizations are used to eliminate large quantities of scripts in order to improve run time. Phases produce intermediate results that can be used by subsequent phases to reduce complexity. A report is generated listing problems for the computer system with corrective actions.

Abstract: Provided is a method, system, program, and data structure for determining patches to apply to a computer system, wherein the patch includes content to add to the computer. A realization list of realization identifiers corresponds to realizations associated with the computer, wherein each realization defines a state of the computer. A realization database includes realization objects, wherein each realization object is uniquely identified by a realization identifier of one realization and includes a patch list indicating those patches whose installation relates to the computer state defined by the realization. The patch lists are accessed from the realization database for those realization objects whose realization identifiers match the realizations identifiers on the realization list. A determination is made of all the patches on the accessed patch lists. A determination is made from the determined patches on the accessed patch lists those patches that are capable of being installed on the computer.

Abstract: A method is provided for controllably delivering signals on a bus, wherein the bus is comprised of a first and second segment. The method comprises monitoring the first bus segment for the presence of a first signal being driven thereon. Thereafter, the first signal is repeated on the second bus segment. To prevent the repeated signal from being repeated again, the second bus segment is not monitored during the repeating phase of the operation.

Abstract: A self-correcting I/O interface driver scheme uses a delay difference detector to detect a difference in delays between an I/O data path and an I/O clock path. The delay difference detector inputs signals from a data output pin connected to the I/O data path and a clock output pin connected to the I/O clock path. Upon determining a delay difference between the signals from the data and clock output pins, the delay difference detector generates signals to one or more drivers in the I/O data path and the I/O clock path. These signals from the delay difference detector are used to effectively adjust delays of the one or more drivers in order to effectively reduce the delay difference between the I/O data path and the I/O clock path.

Abstract: A computer system including a processor, an object cache operatively connected to the processor, a memory, and a translator interposed between the object cache and the memory, wherein the translator maps an object address to a physical address within the memory.

Abstract: A graphics system applies multiple layers of texture information to triangles. The graphics system includes a hardware accelerator, a frame buffer and a video output processor. The hardware accelerator receives vertices of a triangle, identifies fragments of a sampling space which intersect the triangle, and applies the multiple layers of texture to the intersecting fragments. The multiple layers of textures may be stored in a texture memory external to the hardware accelerator. The hardware accelerator switches to a next texture layer after applying the textures of a current layer to all the fragments of the triangle. The hardware accelerator includes (or couples to) a texture accumulation buffer which stores color values associated with the triangle fragments between the application of successive texture layers. The frame buffer stores the samples and pixels generated from the samples by filtration. The video output processor transforms the pixels into a video signal.

Abstract: A method and apparatus for selecting attachments. When a sender indicates in an e-mail application or applet that an attachment is to be associated with an e-mail message, an attachment chooser window is presented. The attachment chooser window provides a browser-based graphical user interface (GUI) which allows a sender to browse data resources, such as HTML documents and associated links. An attachment mechanism is provided by which a sender can choose a currently displayed data resource for attachment in an e-mail message. In one embodiment, the attachment mechanism allows a user to select whether the attachment is retrieved and attached to an e-mail message as a resource locator (such as a URL) of the chosen data resource, or whether source data of the data resource is retrieved and attached to the e-mail message as one or more source files.

Abstract: System and method for enabling application server request failover. For each application server request to be performed by a client computer, a requesting thread may be operable to utilize a custom wire-level communication protocol. Request failure detection mechanisms may be built into the custom wire-level communication protocol so that a requesting thread detects a failed request much sooner than if the thread utilized a standard communication protocol and relied on the client computer operating system for notification of failed requests. After sending a request to an application server, a requesting thread may be operable to “sleep” and then periodically wake up to poll the application server computer to determine whether the request has failed. If the requesting thread receives a response from the application server computer indicating that the request is not currently being processed, then the requesting thread may re-send the request.

Abstract: An electromagnetic (EM) shielding assembly includes an electrically conductive shielding portion and one or more electrically conductive protrusions for engaging with respective conductive apertures in a circuit board. The electrically conductive protrusions can be in electrical communication with the EM shielding portion. The protrusions can enable the EM shielding assembly to be attached to a circuit board in a computer system while also providing an electrical connection to logical ground. Further components, for example a heat sink that may be in electrical communication with the EM shielding portion, may thereby also be connected to logical ground.

Abstract: One embodiment of the present invention provides a system that facilitates self-correcting memory in a shared-memory system. The system includes a main memory coupled to a memory controller for reading and writing memory locations and for marking memory locations that have been checked out to a cache. The system also includes a processor cache for storing data currently in use by a central processing unit. A communication channel is coupled between the processor cache and the memory controller to facilitate communication. The memory controller includes an error detection and correction mechanism and also includes a mechanism for reading data from the processor cache when a currently valid copy of the data is checked out to the processor cache. When the data is returned to the memory subsystem from the cache, the error detection and correction mechanism corrects errors and stores a corrected copy of the data in the main memory.

Abstract: A computer system comprises a plurality of modules and a shift register having a plurality of slots connected in series, wherein each of the plurality of slots is coupled to one of the plurality of modules. In one embodiment, an output of a last slot of the plurality of slots is coupled to an input of an initial slot of the plurality of slots to form a ring. Each slot of the shift register corresponds to a time slot on the ring, and each of the time slots is assigned to one of the modules. At least two of the modules are configured to independently generate frames for transmission on the ring. In another embodiment, at least one of the modules comprises a bridge module coupled to communicate with other bridge modules separate from the plurality of modules.

Abstract: A computer-based system for solving a system of nonlinear equations specified by a vector function, f, wherein f(x)=0 represents ƒ1(x)=0, ƒ2(x)=0, ƒ3(x)=0, . . . , ƒn(x)=0, wherein x is a vector (x1, x2, x3, . . . xn). The system operates by receiving a representation of an interval vector X=(X1, X2, . . . , Xn), wherein for each dimension, i, the representation of Xi includes a first floating-point number, ai, representing the left endpoint of Xi, and a second floating-point number, bi, representing the right endpoint of Xi. For each nonlinear equation ƒi(x)=0 in the system of equations f(x)=0, each individual component function ƒi(x) can be written in the form ƒi(x)=g(x?j)?h(x) or g(x?j)=h(x), where g can be analytically inverted so that an explicit expression for x?j can be obtained: x?j=g?1(h(x)). Next, the system substitutes the interval vector element Xj into the modified equation to produce the equation g(X?j)=h(X), and solves for X?j=g?1(h(X)).

Abstract: Broadly speaking, a method and an apparatus are provided for implementing and performing wireless communication. More specifically, a Java based client application is operated on a wireless device having either a connected limited device configuration (CLDC) or a connected device configuration (CDC). A connection is established between the Java based client application and a server. Data is then transmitted through the connection between the Java based client application and the server.

Abstract: A system and method for reducing the number of memory accesses by a hardware device to a descriptor memory is disclosed. Methods, systems and articles of manufacture consistent with the present invention enable software to embed a subsequent descriptor it is posting in the descriptor memory into a current descriptor listed in the descriptor memory. Additionally, hardware is configured to transmit a data packet associated with the current descriptor to a recipient device. When hardware receives an acknowledgment message from the recipient device associated with the transmitted data packet, it fetches the current descriptor to update a completion code within the current descriptor using a Read-Modify-Write (RMW) transfer sequence. As part of the RMW memory operation, hardware may use the embedded copy of the subsequent descriptor within the current descriptor to transmit the next data packet associated with the subsequent descriptor.

Abstract: A system and method are provided for resynchronizing a media stream. A media streaming server receives live or pre-recorded media for streaming to clients. When media is not received or available for streaming at the appropriate media time index, the media stream is deemed to be out of synchronization. The server selects a future time index at which to resynchronize the stream and may discard intervening media. Media corresponding to the new time index is requested or retrieved and, if available at the new time index, media streaming resumes in synchronization. If media corresponding to the new time index is not available, the server may select another future time index and try again to resynchronize. Resynchronization may be attempted a configurable number of times and, if unsuccessful, the server may terminate the stream.

Abstract: Methods and apparatus for power managing IDE devices. A driver is coupled to a switch, the driver receiving a control signal from a computer system, the control signal indicating whether the computer system is in a power-save mode. The driver drives the switch which generates an output control signal to an IDE device. When the operating system detects that the computer system has been idle for a certain period of time, the operating system toggles the control signal that feeds into the driver which shuts off the switch so that power feeding to the IDE device is shut off.

Abstract: A rack for an electronics assembly may have a supporting frame and a slider mechanism with a first part that is supported by the frame and a second part that supports the electronics assembly. The slider mechanism may be configured to allow the assembly to be moved out of the rack. The rack may further include a cable management system for supporting cables located at the rear of the assembly. The cable management system may have an articulated arm with a first end coupled to the assembly and a second end coupled to the first part of the slider mechanism so that bending of the arm accommodates movement of the electronics assembly. The cable management system may allow the assembly to be pulled out of the rack by the required distance irrespective of the depth of the rack.