Abstract: A method and apparatus for dynamically reconfiguring a computing system are disclosed. The method comprises detecting a predetermined condition triggering a reconfiguration of the computing system; and dynamically reconfiguring a signal path affected by the condition from a first mode to a second mode responsive to detecting the condition. The apparatus is a computing system, comprising: a plurality of I/O switches, a crossbar switch, a plurality of signal paths; and a system controller. Each signal path is defined by an I/O switch and the crossbar switch. The system controller is capable of detecting a predetermined condition triggering a reconfiguration and dynamically reconfiguring at least one of the signal paths affected by the condition from a first mode to a second mode.

Abstract: One embodiment of the present invention provides an integrated circuit assembly module, including a first semiconductor die and a second semiconductor die, each semiconductor die with an active face upon which active circuitry and signal pads reside and a back face opposite the active face. The first and second semiconductor dies are positioned face-to-face within the assembly module so that signal pads on the first semiconductor die overlap with signal pads on the second semiconductor die, thereby facilitating capacitive communication between the first and second semiconductor dies. Additionally, the first and second semiconductor dies are pressed together between a first substrate and a second substrate so that a front side of the first substrate is in contact with the back face of the first semiconductor die and a front side of the second substrate is in contact with the back face of the second semiconductor die.

Abstract: A system and method is provided for minimizing read-only data retrieval time and/or area through the use of combinatorial logic. In one embodiment of the present invention, two address bits are provided to a binary logic function device. The binary logic function device uses the two address bits and predetermined logic functions (i.e., functions that represent a plurality of read-only data values) to produce a binary value—which is the requested read-only data. In another embodiment, the binary values produced by the binary logic function device are provided to at least one multiplexer. The at least one multiplexer uses at least a portion of the remaining bits (i.e., the address bits not being provided to the binary logic function device) to select (or narrow down) which binary values may be the read-only data requested. If the output of the at least one multiplexer contains more than one binary value, then those values are provided to at least one other multiplexer.

Abstract: In a modular computer system comprising at least one information processing module removably received at a first face of a housing, at least one computer support module removably received at a second face of the housing, and at least one power supply module removably received at the second face of the housing, a connections member is provided. The connections member comprises at least one connector at a first face of the member arranged to connect to a connector of the at least one information processing module. The connections member further comprises at least one connector at a second face of the member arranged to connect to a connector of the at least one computer support module. The connections member also comprises at least one connector at the second face of the member arranged to connect to a connector of the at least one power supply module.

Abstract: In the Retirement Payload Array (RPA) of a microprocessor, the pointer advance signal “ADVANCE POINTER” from the Instruction Retirement Logic (IRL) of the Instruction Scheduling Unit (ISU) is utilized to provide conditional read RPA signals. Consequently, according to the invention, a read of the RPA is completed only if it is determined that the read word line being read in the current cycle is not the same read word line that was read in the previous cycle.

Abstract: A distributed shared memory multiprocessor computer system utilizes page placement policies to reduce data access latencies. Pages of memory are allocated to nodes in a distributed shared memory multiprocessor computer system. A placement policy database is maintained which indicates a placement policy for each page in the system. Upon an access to a page, the placement policy corresponding to the accessed page is determined and the indicated policy is acted upon. A Migrate on Next Touch policy provides that the next access to a page with this policy will cause the page to migrate to the node of the accessing CPU. A Memory Follows Lightweight Process (LWP) policy ensures that pages within a given address range are always local to a specified LWP. A Migrate on Every Touch policy provides that pages within a given address range are migrated to an accessing CPU on every touch. A Replicate on Remote Touch policy provides for replication of a page in the memory of each accessing CPU's domain.

Abstract: A method of testing a graphical user interface includes selecting a widget of the graphical user interface, associating an access mode with the widget, generating a mode-specific input message based on the widget and the access mode, sending the mode-specific input message to the graphical user interface, detecting a mode-specific response from the graphical user interface using a detection tool, and evaluating the graphical user interface based on the mode-specific response.

Abstract: A bi-directional input/output (IO) cell for transmitting and receiving data signals simultaneously over a single line. The bidirectional IO cell having an IO node adapted to connect to the line. A driver has an output connected to the line and an input for receiving a core output signal. A first differential amplifier has a first input connected to the IO node and a second input connected to a high voltage reference circuit. A second differential amplifier has a first input connected to the IO node and a second input connected to a low voltage reference circuit.

Abstract: A semiconductor device verification system and method isolates errors detected during verification by comparing a predetermined stimulus applied to the semiconductor device with an observed stimulus measured within the semiconductor device. If the predetermined stimulus differs from the observed stimulus, the error likely results from an inaccuracy in the verification process rather than a flaw of the semiconductor device. The observed stimulus is measured between the input circuit and the core of the semiconductor device, such as between the flip flop associated with an input pin and the logic core of a processor. An observed stimulus circuit integrated within the semiconductor device outputs the observed stimulus to an output pin for use by an error isolation engine associated with verification testing equipment.

Abstract: A chip package for reduced EMI. In one embodiment, a chip package includes a semiconductor chip mounted on a substrate. First and second horizontal conductors may be present within the substrate. The semiconductor chip is coupled to the first and second horizontal conductors by a first and second pluralities of vertical conductors, respectively. The silicon chip may receive power via the first horizontal conductor and the first plurality of vertical conductors. The first and second horizontal conductors are connected to external connectors by third and fourth pluralities of vertical conductors, respectively. One or more capacitors may be electrically coupled between the first and second horizontal conductors.

Abstract: Manipulation of a multi-wide object class design layout to facilitate design rule checking or automatic correction of design rule errors is improved by deriving wide class objects from geometries of the design layout, and applying certain rules to non-virtual boundaries of the wide class objects that are not applied to virtual boundaries of the wide class objects. In an exemplary embodiment, the wide class objects are preferably derived by sizing down, then sizing up, each geometry by a sizing factor equal to half the minimum width of the particular wide class object less an amount that preferably corresponds to that represented by a minimum resolution of the design layout. Portions of a geometry that are otherwise excluded as being too narrow in width, but that lie wholly within a correction factor of the boundary of the wide class object otherwise derived, are preferably included to form effective wide class objects.

Abstract: Techniques for integrating Information Systems with Application Servers are disclosed. The techniques can be used to implement a configurable connector interface that connects to existing interfaces used to access various Information Systems. The configurable connection interface can encapsulate these existing interfaces. Accordingly, the configurable connector interface can serve as a standard interface that can be used to connect an application server to various Information Systems. The configurable connection interface can be implemented as a “Resource Adaptor” that can be modified to fit the requirements of a particular existing interface used to access a particular information system (e.g., a database driver developed for a particular relational database). A Graphical User Interface (GUI) can be used to conveniently modify and deploy the modified Resource Adaptor file. These operations can conveniently be performed by using a deployment tool through a Graphical User Interface (GUI).

Abstract: In one general aspect, a network communication unit is disclosed that includes connection servicing logic that is responsive to transport-layer headers and is operative to service virtual, error-free network connections. A programmable parser is responsive to the connection servicing logic and is operative to parse application-level information received by the connection servicing logic for at least a first of the connections. Also included is application processing logic that is responsive to the parser and operative to operate on information received through at least the first of the connections based on parsing results from the parser.

Abstract: A processor chip is provided. The processor chip includes a plurality of processing cores, where each of the processing cores are multi-threaded. The plurality of processing cores are located in a center region of the processor chip. A plurality of cache bank memories are included. A crossbar enabling communication between the plurality of processing cores and the plurality of cache bank memories is provided. The crossbar includes an arbiter configured to arbitrate multiple requests received from the plurality of processing cores with available outputs. The arbiter includes a barrel shifter configured to rotate the multiple requests for dynamic prioritization, and priority encoders associated with each of the available outputs. Each of the priority encoders have logic gates configured to disable priority encoder outputs. A method for arbitrating requests within a multi-core multi-thread processor is included.

Abstract: In a method for dynamic allocation of memory address space, an original version of a program is executed. This execution includes the execution of a request to use memory address space occupied by an optimized version of the program that is protected from modification. When this request is detected, execution control is passed to an optimization code that was used to define the optimized program. The optimization code copies a portion of the optimized program residing in the memory address space requested by the original program, writes the copied portion to unallocated memory address space, and adjusts the code of the optimized program. The protection of the copied portion of the optimized program is released, and execution control is returned to the original program. The request to use the memory address space occupied by the portion of the optimized for which the protection has been released is then re-executed.

Abstract: In one general aspect, a network communication unit is disclosed that includes connection servicing logic that is responsive to transport-layer headers and is operative to service virtual, error-free network connections. A programmable parser is responsive to the connection servicing logic and is operative to parse application-level information received by the connection servicing logic for at least a first of the connections. Also included is application processing logic that is responsive to the parser and operative to operate on information received through at least the first of the connections based on parsing results from the parser.

Abstract: A method of utilizing timestamps for the global ordering of event information, particularly hardware error reporting, is disclosed. Locally generated time stamps are associated with hardware errors or other events. The timestamps form the basis for the global ordering of event information. The timestamps are normalized, either through a pre-synchronization process with a common time, or through the use of offsets maintained either locally near system chips or by the system processor. Once normalized, the timestamps can be compared to determine a first occurring event among multiple reported events.

Abstract: The present invention provides a method and apparatus for distributed intraframe transmission. In one embodiment of the present invention, digital images are divided into regions. In this embodiment, an I-frame is not transmitted all at once. Instead, in each transmission, a region of the image is compressed without using interframe compression while the rest of the image is compressed using interframe compression. The region transmitted without interframe compression changes with each transmission. Thus, over the course of several transmissions every region of the image is transmitted without interframe compression. A transmission schedule controls the transmission of I-frame data for an entire image over the course of several frame transmissions. In one embodiment, a digital image is divided into M regions, and one region is transmitted without using interframe compression in each frame.

Abstract: A system and method for rendering a polygon, such as a triangle. The method may comprise receiving geometry data (or vertex data) defining vertices of the polygon. The method may compute initial vertex x,y values at end points proximate to each of the vertices of the polygon, and a slope value along each edge of the polygon. The computed slope may be a quantized slope value having a first number of bits of precision. The first number of bits of precision may produce inaccuracies for interpolated x,y values computed at the end points of an edge of the polygon. The method may then interpolate x,y values along each respective edge of the polygon using the computed slope along the respective edge of the polygon. Finally the method may store final x,y values for each respective edge of the polygon. The final x,y values comprise the interpolated x,y values for non-end points of the respective edge, and the computed initial vertex x,y values for each of the end points of the respective edge.

Abstract: A rack for an electronics assembly comprises: (i) a supporting frame (22, 24); (ii) a slider mechanism (4) having a first part (6) that is supported by the frame and a second part (8) that supports the electronics assembly, the mechanism configured to allow the assembly to be moved out of the rack; and (iii) a cable management system for supporting cables located at the rear of the assembly. The cable management system comprises an articulated arm having a first end coupled to the assembly and a second end coupled to the first part (6) of the slider mechanism so that bending of the arm accommodates movement of the electronics assembly. The cable management system ensures that the assembly can be pulled out of the rack by the required distance irrespective of the depth of the rack.