Abstract: Three-dimensional compressed geometry is decompressed with a unit having an input FIFO receiving compressed data bits and outputting to an input block state machine and an input block, whose outputs are coupled to a barrel shifter unit. Input block output also is input to Huffman tables that output to the state machine. The state machine output also is coupled to a data path controller whose output is coupled to a tag decoder, and to a normal processor receiving output from the barrel shifter unit The decompressor unit also includes a position/color processor that receives output from the barrel shifter unit. Outputs from the normal processor and position/color processor are multiplexed to a format converter. For instructions in the data stream that generate output to the format converter, the decompression unit generates a tag sent to the tag decoder in parallel with bits for normals that are sent to the format converter.

Abstract: A sense amplifier type input receiver includes a differential receiver circuit operatively coupled to an output stage. The output stage includes a pass gate enabled latch. The differential receiver circuit may output a first differential output and a second differential output. The output stage may include a first pass gate operatively coupled between the first differential output and an output of the output stage, a second pass gate operatively coupled between the second differential output and the pass gate enabled latch, and the pass gate enabled latch may be operatively coupled to the output of the output stage.

Abstract: A method for controlling thermal cycles in a computer system is provided. The method is comprised of receiving a request to transition the computer system from a first operating mode to a second operating mode, where less power is consumed in the second operating mode. A historical rate at which the computer system has transitioned between the first and second operating modes is determined, and the requested transition is permitted in response to the historical rate being less than a first preselected setpoint, but denied in response to the historical rate being greater than the first preselected setpoint.

Abstract: A graphics system comprises a rendering unit, a sample buffer and a sample-to-pixel calculation unit. The rendering unit receives graphics data specifying three triangle vertices, generates sample positions, and determines which samples reside inside the triangle. The rendering unit computes an axial rate of change of an ordinate based on the positions and ordinates of the vertices, and, for each sample residing inside the triangle, (a) multiplies the axial rate by a edge-relative sample displacement resulting in a first product, (b) interpolates a projection value for a projection point on a first edge of the triangle, and (c) adds the first product to the projection value resulting in a sample ordinate value. The sample buffer stores the sample ordinate value the samples inside the triangle. The sample-to-pixel calculation unit reads sample ordinate values from the sample buffer and generates a pixel value by filtering the sample ordinate values.

Abstract: Provided is a method, system, and program for managing access to data objects by multiple user programs over a network. A page is generated including at least one editable field of data from at least one data object. An initial value is calculated from the at least one data object and the page and the initial value are transmitted to one user program over the network. The page and the initial value are received from the user program, wherein the received page includes modified data in at least one editable field. A current value is calculated from the at least one data object after receiving the page and a determination is made as to whether the initial value transmitted with the received page is different than the current value. If the initial and current values match, then the data object is updated with the modified data included in the received page.

Abstract: A method for using a Synchronization Interface in a computer system compliant with a CORBA Object Transaction Service or a Java Transaction API (such as Java 2 Platform Enterprise Edition Reference Implementation) to perform internal state clean up in containers associated with a completed transaction. First, a synchronization object is registered for each new transaction in a container with a Transaction Manager. The Transaction Manager detects a completion of the transaction and then invokes an “after_completion” operation (method) on the synchronization object. This notifies each container involved in the completed transaction to perform internal memory space clean up. Thus, the method uses an existing Synchronization Interface mechanism to perform internal memory state clean up in containers, without adding additional communication mechanisms.

Abstract: A data storage subsystem including a storage disk array employing dynamic data striping. A data storage subsystem includes a plurality of storage devices configured in an array and a storage controller coupled to the storage devices. The storage controller is configured to store a first stripe of data as a plurality of data stripe units across the plurality of storage devices. The plurality of data stripe units includes a plurality of data blocks and a parity block which is calculated for the plurality of data blocks. The storage controller is further configured to store a second stripe of data as a plurality of data stripe units across the storage devices. The second plurality of data stripe units includes another plurality of data blocks, which is different in number than the first plurality of data blocks, and a second parity block calculated for the second plurality of data blocks. Furthermore, the second plurality of data blocks may be a modified subset of the first plurality of data blocks.

Abstract: One embodiment of the present mechanism provides a system to facilitate testing of garbage collection implementations. The system operates by first receiving a trace of valid memory transactions at a test harness. This trace of valid memory transactions is replayed through the test harness into a memory manager, which includes a garbage collection implementation under test. The results of replaying this trace are then observed to verify that the garbage collection implementation under test does not erroneously change the contents of the memory.

Abstract: Performance of an integrated circuit design, whether embodied as a design encoding or as a fabricated integrated circuit, can be improved by selectively substituting low Vt transistors in a way that prioritizes substitution opportunities based on multi-path timing analysis and evaluates such opportunities based on one or more substitution constraints. By valuing, in a prioritization of substitution opportunities, contributions for all or substantially all timing paths through the substitution opportunity that violate a max-time constraint, repeated passes through a timing analysis phase can be advantageously avoided or limited. In addition, by recognizing one or more constraints on actual low Vt substitutions, particular noise-oriented constraints, the scope of post substitution design analysis can be greatly reduced. In some realizations, substitutions are performed so long as a leakage current budget is not expended.

Abstract: Clocked half-rail differential logic circuits are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock. The addition of the sense amplifier circuit, and second delayed clock signal, allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic block to provide a driver function. Consequently, the clocked half-rail differential logic circuits of the invention are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art half-rail differential logic circuits.

Abstract: An apparatus and method are provided for identifying functionally sensitized data paths in a logic circuit and storing the identified data paths in a representation of the logic circuit. The representation of the logic circuit includes a single occurrence of each identified data path along with a variable for each single name or path segment identified. The variable represents a number of times that path segment or signal name was functionally sensitized.

Abstract: An elongate gasket that can be placed on an electrical assembly in order to reduce electromagnetic interference, comprises (i) an elongate deformable strip (1) of electrically conductive material that has been folded along its length to form an arcuate cross-sectional profile; and (ii) an attachment arrangement (10, 12) to secure the gasket onto the component; At least one of the strip and the attachment arrangement is folded at an end region (30) thereof over the end of the other of the strip and the attachment arrangement in order to provide a smoothly varying longitudinal profile at the end of the gasket. This form of gasket allows components such as modules, to be inserted into recesses in an assembly by sliding along the gasket without damage to the gasket or causing it to be shifted.

Abstract: A method for transmitting messages between two processes includes creating a communications channel between a first channel adapter coupled to a client process and a second channel adapter coupled to a remote process. The method further includes reading a request message at the first channel adapter, segmenting the request message into a series of packets, assigning a sequence number to each packet, and transmitting the packets in order to the second channel adapter through the communications channel. The method further includes receiving the packets at the second channel adapter and sending at least one acknowledgement message to the first channel adapter in response to the received packets.

Abstract: An authoring system prepares a specified set of classes for preloading in client devices lacking a virtual memory manager. The authoring system converts the specified set of classes into a plurality of resource modules, a subset of the resource modules each including items that have pointers to items in other ones of the resource modules. The authoring system generates a load module, for loading into the client devices, that includes the plurality of resource modules, an interpreter and a startup procedure. The interpreter is for executing, on the client devices, programs in a predefined computer language. The specified set of classes includes methods in the predefined computer language. The startup procedure is for execution by the client devices when loading the interpreter for execution. The startup procedure replaces pointers in the resource modules with updated pointers in accordance with actual memory locations of the resource modules in any particular one of the client devices.

Abstract: A method and apparatus for compensating for tunneling leakage current through a first capacitor includes: an operational amplifier, connected in a negative feedback configuration; a first compensation transistor; a second compensation transistor; and a compensation capacitor. The compensation capacitor is chosen so that the ratio of the area of the compensation capacitor divided by the area of the first capacitor is an area ratio “AR”. The operational amplifier sets the gate voltage of the compensation capacitor to be the same as the gate voltage of the first capacitor. The ratio of the size of the second compensation transistor divided by the size of the second compensation transistor is also the area ration “AR”.

Abstract: A system and method for synchronizing mirrored and striped disk writes. A data storage system may include a client computer system coupled to a first data storage device and a second data storage device and configured to transmit a first data write request. The first storage device may be configured to transmit a sequence number to the client computer system in response to receiving the first data write request. The client computer system may be further configured to transmit a second data write request including the sequence number to the second storage device. The second data storage device may include a counter and is configured to compare a current counter value to the sequence number. If the counter value is equal to the sequence number, the second storage device stores the data bytes corresponding to the second data write request and increments its counter.

Abstract: A method for processing a computer software process including a task file is provided. The method includes designating a group of available processing resources to execute the task file that includes task groups with each task group including a plurality of tasks. The method also includes scheduling the task groups in the task file for execution with a plurality of remaining processing resources, each running a client controller component code. Further included is obtaining access to a set of free remaining processing resources of the plurality of remaining processing resources, each having a set of criteria matching a set of requirements of each task in a particular task group. The method also includes executing tasks in the particular task group when access to all the free remaining resources in the set of the free remaining processing resources have been granted. Also included is generating an execution result report.

Abstract: In an embodiment, present application describes a system and method to detect the alignment of multiple clocks in multi-clock domains system. In some variations, multiple clocks are derived from one or more reference clocks using various PLLs. The derived clocks maintain frequency relationship with the reference clock. In some variations, a relationship between the frequencies of various clocks is used to generate the alignment signals in the domain of one of the clocks.

Abstract: A system and method of predicting network data traffic includes coupling a first group of clients to a current server that results in a current CPU utilization of the current server. A second group of clients are coupled to the current server. A load multiple is determined and the current CPU utilization is compared to a predicted CPU utilization. A server requirement is increased if the current CPU utilization is greater than or equal to the predicted CPU utilization.