Abstract: A small footprint device can securely run multiple programs from unrelated vendors by the inclusion of a context barrier isolating the execution of the programs. The context barrier performs security checks to see that principal and object are within the same context or to see that a requested action is authorized for an object to be operated upon. Each program or set of programs runs in a separate context. Access from one program to another program across the context barrier can be achieved under controlled circumstances by using an entry point object.

Abstract: The present invention integrates data prefetching into a modulo scheduling technique to provide for the generation of assembly code having improved performance. Modulo scheduling can produce optimal steady state code for many important cases by sufficiently separating defining instructions (producers) from using instructions (consumers), thereby avoiding machine stall cycles and simultaneously maximizing processor utilization. Integrating data prefetching within modulo scheduling yields high performance assembly code by prefetching data from memory while at the same time using modulo scheduling to efficiently schedule the remaining operations. The invention integrates data prefetching into modulo scheduling by postponing prefetch insertion until after modulo scheduling is complete. Actual insertion of the prefetch instructions occurs in a postpass after the generation of appropriate prologue-kernel-epilogue code.

Abstract: The present invention provides an entropy coding scheme using an adaptable prefix code. The prefix code is a binary representation of the algorithm used to compress and decompress the data. There are prefix zeros that represent the number of significant binary digits that follow the first one. According to one embodiment, this scheme works on both positive and negative integers and encodes lower order integers with a smaller length of codeword. In another embodiment, the zero integer is encoded as a special case with the shortest codeword. In yet another embodiment, the present scheme is preferred by data sets that are clustered about zero, such as image data sets that have been transformed via a wavelet transform or a discrete cosine transform.

Abstract: A dual mode memory module includes an interface configured to receive a first memory module, a first control circuit for switching between unbuffered and registered/buffered modes, an interface configured to receive a second memory module, and a second control circuit for switching the operation of the second memory module between unbuffered and registered/buffered modes. The control circuit may include a bus switch and a register/buffer operatively coupled to the bus switch. Enable/disable pins may be included operatively coupled to the first bus switch and the first register/buffer and configured so that only one of the first bus switch and the first register/buffer is active at a time. A system controller for detecting a type of memory module connected to the stackable dual mode memory interface and enabling one of the bus switch and register/buffer based on the type of memory module detected may be included.

Abstract: One embodiment of the present invention provides a system for analyzing post-mortem information specifying a state of the remote computer system after the failure of the remote computer system. The system operates by receiving a code module sent from a debugging computer system at the remote computer system. The remote computer system executes the code module, and allows the executing code module to read the post-mortem information from the remote computer system. The remote computer system also allows the executing code module to generate a result, and returns the result to the debugging computer system. In one embodiment of the present invention, the code module includes platform-independent JAVA byte codes that are executed on a JAVA virtual machine located on the remote computer system. In one embodiment of the present invention, the system allows a user of the remote computer system to specify a security policy for the executing code module.

Abstract: A system and method providing address broadcast synchronization using multiple switches. The system for concurrently providing addresses to a plurality of devices includes a first switch and a second switch. The first switch is coupled to receive address requests from a first plurality of sources. The first switch is configured to output the address request from the first plurality of sources. The second switch is coupled to receive address requests from a second plurality of sources. The second switch is configured to receive the address request from the first plurality of sources from the first switch. The second switch is further configured to delay the address request from the second plurality of sources prior to arbitrating between ones of the address request from the second plurality of sources and ones of the address request from the first party of sources received from the first switch.

Abstract: A method for tracking assertions in an application is provided. The method includes providing a specification for the application, identifying each assertion in each chapter of the specification, and generating a markup language document. The specification is divided into chapters, which define functional aspects of the application. The markup language document has an associated tagged entry for each of the identified assertions. Each tagged entry has an identifier tag which correlates the tagged entry to a specific chapter of the specification.

Abstract: A system and method for isolating the execution of a plurality of applications. The applications may utilize or share one or more “original” classes. Only one copy of each original class is maintained, regardless of how many applications utilize it. Static fields are extracted from the original classes. A separate copy of the static fields is created for each of the utilizing applications. A static field class which includes instance fields corresponding to the static fields may be created, wherein each instance of the static field class corresponds to one of the utilizing applications. Access methods for the one or more static fields may be created, wherein the access methods are operable to access the corresponding separate copy of the static fields based upon the identity of the utilizing application.

Abstract: Virtual registers are mapped to architectural or physical registers according to a register map that is configurable with software. In one embodiment, only privileged software can configure the register map. In another embodiment, a portion of the register map is configurable with non-privileged software, and another portion is only configurable with privileged software. In yet another embodiment the register map is fully configurable by user software. The configurable register map provides backwards compatibility to code written for hardware-defined register mapping, while allowing flexible approaches to register mapping in code generated for a processor architecture using a software controllable register map.

Abstract: The analysis of the lifetime of objects in a garbage-collected system may be accomplished quickly and effectively using reference counts and cyclic garbage analysis. A reference count is maintained for each of the objects to indicate the number of incoming pointers. Each time the graph structure is altered, the reference counts are updated. Timestamps are recorded each time the reference count for objects change. If a reference count goes to zero, the corresponding object may be indicated as dead. A garbage collection need only be run once (perhaps at the end), and after it is run the system may indicate which objects are cyclic garbage. The timestamps for objects which are cyclic garbage are then reviewed in reverse chronological order. For each timestamp found, the corresponding object and any object reachable from the corresponding object are indicated as dead. These objects are then removed from the set of cyclic garbage.

Abstract: A method for controlling access to deprecated methods of an implementation is provided. The method includes receiving a request to access a method that has been marked as deprecated and building a call stack for the request. Also included is inspecting the call stack to determine if the request is from an application outside of the implementation. The method further includes acting on the request in accordance with a control policy defined by a pluggable policy.

Abstract: An improved lookup service is provided that allows for the dynamic addition and deletion of services. This lookup service allows for the addition and deletion of services automatically, without user intervention. As a result, clients of the lookup service may continue using the lookup service and its associated services while the updates occur. Additionally, the lookup service provides a notification mechanism that can be used by clients to receive a notification when the lookup service is updated. By receiving such a notification, clients can avoid attempting to access a service that is no longer available and can make use of new services as soon as they are added to the lookup service.

Abstract: A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.

Abstract: Methods, systems, and articles of manufacture consistent with certain principles related to the present invention enable a computing system to receive a serialized message including a target object that is associated with at least one member object. The computing system may invoke a deserialize method on a deserializer associated with the target object. In the event the deserialize method cannot completely deserialize the target object, the deserializer may configure a state object returned by the method to monitor a deserialization status associated with the at least one member object. The deserializer may also create an instance builder object that may complete deserialization of the target object in response to receiving a notification reflecting that the at least one member object is deserialized.

Abstract: A novel processor chip (10) having a processing core (12), at least one bank of memory (14), an I/O link (26) configured to communicate with other like processor chips or compatible I/O devices, a memory controller (20) in electrical communication with processing core (12) and memory (14), and a distributed shared memory controller (22) in electrical communication with memory controller (20) and I/O link (26). Distributed shared memory controller (22) is configured to control the exchange of data between processor chip (10) and the other processor chips or I/O devices. In addition, memory controller (20) is configured to receive memory requests from processing core (12) and distributed shared memory controller (22) and process the memory request with memory (14). Processor chip (10) may further comprise an external memory interface (24) in electrical communication with memory controller (20). External memory interface (24) is configured to connect processor chip (10) with external memory, such as DRAM.

Abstract: Clocked charge recycling differential logic circuits are activated by a delayed clock. According to the invention, when clocked charge recycling differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked charge recycling differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked charge recycling differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked charge recycling differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked charge recycling differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.

Abstract: A method of selecting a security model for an organization operating an application on the organization's computer network is described. A current strength level for a countermeasure is determined based on input data and rules corresponding to the application. The method and apparatus determine a recommended strength level for countermeasures based on the input data and security risk data. Based on the current strength level and the recommended strength level, the method determines and outputs a security model including a countermeasure and corresponding strength level. The method may also modify the model based on exception conditions. The method may be used to calculate the risk of attack to the application and degree to which the organization conforms to industry practices.

Abstract: Methods and systems consistent with the present invention provide a family of networks ranging from 2 nodes to 16 nodes that can be partitioned in an unconstrained manner. That is, where the number of nodes in one of these networks is N, subnetwork can contain any number of nodes from 1 to N−1 as long as the total number of nodes in both subnetworks equals N. Furthermore, each subnetwork can be partitioned repeatedly until reaching the atomic level (i.e., when the subnetwork contains a single node). In accordance with methods and systems consistent with the present invention, when a network is partitioned, each subnetwork has various desirable properties. For example, the maximum path length between any two nodes in each subnetwork nodes is 3, and each to subnetwork has a set of deadlock-free routings.

Abstract: Provided are a method, system, and program for servicing customer requests for at least one product. At least one queue is maintained in a service computer indicating at least one customer requesting product support for the at least one product. Requests for customer service are received from customer computers used by customers over a network. Transmitted to the customer computers of customers indicated in the queue is chat session content between a technical support agent and one customer indicated in the queue.

Abstract: Provided are a computer implemented method, system, and program for translating a class schema in a source language to a target language. Class element definitions in a source file in the source language are received. The definitions of the class elements define instances of metadata types providing metadata for the class elements. Statements in the target language are generated to implement class elements defined in the source file. Statements are generated in the target language to define metadata elements for metadata types. For each metadata data type instance defined with one class element in the source file, at least one statement is generated in the target language to associate the metadata element generated for the metadata type with the implementation of the class element corresponding to the class element defined with the metadata type instance in the source file.