Abstract: A mechanism is disclosed for determining an accelerated test for a device. The method comprises calculating an estimated amount of damage that an element of the device would suffer if the device were operated under a set of specified conditions over a certain period of time (e.g., expected lifetime of the device). The method further comprises determining an accelerated test to which to subject the element in order to cause the element to suffer an actual amount of damage that is approximately equal to the estimated amount of damage. The accelerated test may be an accelerated test cycle, such as an accelerated temperature cycle.

Abstract: A self-updating grid mechanism using peer-to-peer platform protocols. A compute node may send another node information about its compute node configuration using peer-to-peer platform protocols. The other node may be a master node configured to manage a grid of one or more compute nodes, another compute node, or some other peer node. In one embodiment, the other node may be a logically nearby node to the compute node. In one embodiment, the compute node may discover the other node using peer-to-peer platform protocols. The other node may determine if the compute node configuration needs to be updated from the compute node configuration information. If the compute node configuration needs to be updated, the other node may send update information to the compute node using peer-to-peer platform protocols. The compute node may then update its compute node configuration according to the update information.

Abstract: A computer system may include a sending device, a receiving device, and a network coupling the devices. The sending device may be configured to send a packet on the network in order to initiate a transaction. The sending device is configured to only encode a portion of a transaction ID identifying the transaction in the packet. The receiving device is configured to receive the packet from the network and to send a responsive packet to the sending device as part of the transaction. The receiving device is configured to encode all of the transaction ID in the responsive packet. The receiving device may generate the portion of the transaction ID not encoded in the packet by the sending device in response to the packet having a particular characteristic.

Abstract: A method for analyzing a target system that includes obtaining a plurality of characteristics from the target system using a characteristics extractor and at least one selected from the group consisting of a software build project associated with the target system and a modified software build project associated with the target system, wherein the plurality of characteristics is associated with a characteristics model, storing each of the plurality of characteristics in a characteristics store, and analyzing the target system by issuing at least one query to the characteristics store to obtain an analysis result.

Abstract: Method and apparatus for the on-demand localization of files. Embodiments may provide a file format-independent localization mechanism that automates the extraction of localizable text content from localizable files, the process of generating translations for the extracted localizable text content, and the generation of localized versions of the localizable files including the translations for the extracted localizable content. The localized versions of the files may be automatically generated with correct structure and content, correct file names, and automatically placed in correct file locations by the localization mechanism, and are thus readily available to and locatable by an automated build process for the localized version of the product, thus reducing or eliminating the necessity for human intervention during the localization process.

Abstract: A method and apparatus for implementing out-of-order memory transactions in a multithreaded, multicore processor. In the present invention, circular queue comprising a plurality of queue buffers is used to store load data returned by a memory unit in response to a request issued by a processing module, such as a stream processing unit, in a processing core. As requests are issued, a destination queue buffer ID tag is transmitted as part of the request. When the request is returned, that destination number is reflected back and is used to control which queue within the circular queue will be used to store the retuned load data. Separate pointers are used to indicate the order of the queues to be read and the order of the queues to be written. The method and apparatus implemented by the present invention allows out-of-order data to be processed efficiently, thereby improving the performance of a fine grain multithreaded, multi-core processor.

Abstract: One embodiment of the present invention provides a system which creates multiple checkpoints in a processor that supports speculative-execution. The system starts by issuing instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a launch condition during an instruction which causes a processor to enter execute-ahead mode, the system performs an initial checkpoint and commences execution of instructions in execute-ahead mode. Upon encountering a predefined condition during execute-ahead mode, the system generates an additional checkpoint and continues to execute instructions in execute-ahead mode. Generating the additional checkpoint allows the processor to return to the additional checkpoint, instead of the previous checkpoint, if the processor subsequently encounters a condition that requires the processor to return to a checkpoint.

Abstract: Static random access memory (SRAM) cells and methods of operation are provided which may be used to provide improved writeability and stability to support low voltage operation of memory devices. For example, in one implementation, by temporarily interrupting the connection between portions of an SRAM cell and a power source such as a reference voltage or current source, the writeability of SRAM cells can be improved. Additional read port implementations are also provided to facilitate low voltage operation. In another implementation, a power switch circuit responsive to a word line and logic signals may be used to provide such interruptions.

Abstract: A method and a system for request routing may include a router configured to forward a request to a process. The process may acquire a lock on a memory object. If the process is becomes hung, a data synchronizer may release the lock on the memory object assigned to the process. The lock on the memory object assigned to the process may be released after the process is detected to be hung and after another process requests a lock to the memory object. The router may list inactive processes, and if the process is hung, add the process to the list of inactive processes. The router may be configured to check the inactive list and not route requests to processes on the inactive list. The data synchronizer may be configured to prevent processes on the inactive list from modifying data.

Abstract: A method and protocol suitable for mediating communication between an application written in a platform independent language, running on a specific processor or computing platform, and an application written in the processor's native language. As part of the present invention, an application written in a platform independent code may be compiled and/or linked to a first mediation module and an application written in the processor's native code may be compiled and/or linked to a second mediation module The first and second mediation modules may communicate with each other utilizing a stream protocol providing for communication of various data types, including but not limited to function calls, function parameters, function results, and event notification.

Abstract: An approach is provided in embodiments of the present invention for building multiple-output static CMOS logic gate circuits that share transistors when computing multiple functions from a common set of inputs. In particular, an approach is provided which includes building multiple-output static NAND gates that compute the subfunctions of three or more inputs and building multiple-output static NOR gates that compute the subfunctions of two or more inputs. The approach also includes building multiple-output static XOR-XNOR gates that are capable of computing two-input XOR, three-input XOR, two-input XNOR, and three-input XNOR, and building multiple-output static Propagate-Generate (PG) compound gates. The approach further includes building carry propagate adders, priority encoders, binary-to-thermometers, decoders, etc. that are capable of using the multiple-output static gates embodied in the present invention.

Abstract: A method for modeling a database management system involving receiving a query, computing a hit rate value associated with a cache, wherein the hit rate value is computed using a counter group, comparing the hit rate value to a predetermined value to obtain a result, providing a reply to the query if the result is a hit, incrementing a counter in the counter group when the cache is not full and proceeding to a next cache if the result is a miss, and providing a diagnostic output for the database management system.

Abstract: In a computer network, an object identifier relating to the identity of a network component is generated by applying an algorithm to manufacturer's data stored in a memory associated with the component. An MIB correlating the generated object identifier and the component description is produced by applying the same algorithm to corresponding data items in a manufacturer's product database and correlating product description information with the generated object identifier data.

Abstract: A system that provides fault tolerance in a parallel processing system. During operation, the system executes a parallel computing application in parallel across a subset of computing nodes within the parallel processing system. During this process, the system monitors telemetry signals within the parallel processing system. The system analyzes the monitored telemetry signals to determine if the probability that the parallel processing system will fail is increasing. If so, the system increases the frequency at which the parallel computing application is checkpointed, wherein a checkpoint includes the state of the parallel computing application at each computing node within the parallel processing system.

Abstract: A personal authorisation device wearable by a user includes an input operable to receive data for authenticating a user, a memory operable to store validation information derived from the user authentication data, and an output operable to provide an authorisation code. The device further includes a tamper detector that triggers if the device is removed from its wearer. Triggering of the tamper detector serves to disable use of the device.

Abstract: Embodiments of the present invention provide for reliable receipt of data packets by a network device. The present invention also provides a receive thread for receiving data packets. The present invention also provides a drainer thread for processing packets according to an applicable protocol. As a result, the network device is capable of receiving and processing data packets at an increased rate.

Abstract: One embodiment of the present invention provides a system that facilitates proximity communication. This system includes a circuit containing a bootstrap transistor and a pass-gate transistor, where the drain of the bootstrap transistor is coupled to the gate of the pass-gate transistor. Note that a first coupling capacitance exists between the source of the pass-gate transistor and the drain of the bootstrap transistor and a second coupling capacitance exists between the drain of the pass-gate transistor and the drain of the bootstrap transistor. During operation, the gate and the source of the bootstrap transistor are coupled to a high voltage, thereby causing an intermediate voltage at the drain of the bootstrap transistor.

Abstract: A method for tracing an instrumented application, including loading the instrumented application into a kernel level to obtain a corresponding instrumented process, registering a helper action with a tracing framework, tracing the instrumented process using the tracing framework, wherein tracing comprises triggering a probe in the instrumented process, determining whether the helper action is associated with the probe, and performing the helper action if the helper action is associated with the probe.

Abstract: A mechanism is disclosed for implementing a sparse file system for an operating system partition. In one implementation, a non-global partition is created within a global operating system environment. A file system is then established for the non-global partition. This file system may comprise one or more virtual directories, which reference other directories. Referencing other directories in this manner makes it is possible to avoid having to copy all of the files used by processes running in the non-global partition into the file system. As a result, storage and other system resources can be saved.

Abstract: Managing speculative execution via groups of actions corresponding to atomic traces enables efficient processing of flag-related actions, as atomic traces advantageously enable single checkpoints of flags at trace boundaries. Flag restoration from checkpoints for trace aborts uses a flag checkpoint table to store flag checkpoints, each corresponding to an atomic trace. The table is accessed for flag restoration in response to a trace abort. In a first technique, a corresponding flag checkpoint is stored in response to trace renaming, and the flag checkpoints are updated as flags are modified. Flags are restored from the flag checkpoint corresponding to an aborted atomic trace. In a second technique, a corresponding flag checkpoint is allocated to an invalid state in response to trace renaming, and initialized on-demand when flags are first modified in accordance with the atomic trace. Flags are restored from the oldest flag checkpoint starting from an aborted atomic trace.