Abstract: A method for monitoring performance of a mobile device involves intercepting a first monitoring request from a monitoring management host, where the first monitoring request is associated with the mobile device, enabling a monitoring agent associated with the mobile device, establishing a thin listener associated with the monitoring agent, transmitting a second monitoring request, in response to the first monitoring request, to the mobile device, receiving, by the thin listener, data from the mobile device in response to the second monitoring request, analyzing the data received in response to the second monitoring request to obtain an analysis report, and transmitting the analysis report to the monitoring management host, in response to the first monitoring request.

Abstract: The present invention provides methods of checking for duplicate port globally unique identifiers during a discovery of a subnet of a system using a channel adapter. These methods allow a Subnet Manager, an Infiniband entity for managing the Infiniband topology, to detect invalid ports that have matching GUIDs. An additional feature is that a recently added port with a duplicate GUID will not replace an original port with the same GUID, but instead will be left out of the network.

Abstract: A processor that protects an execution pipeline includes a residue-based error detection infrastructure including a first logic for computing a first residue of a result of an executed instruction instance, and a second logic for computing a second residue of the result. The second logic applies arithmetic operations of the executed instruction instance to residues of operands of the instruction instance. The execution pipeline includes registers and one or more arithmetic execution units. A method of protecting an execution pipeline includes performing one or more operations of an instruction instance on residues of operands of the instruction instance, computing a first residue of a result of the operations on the operand residues, computing a second residue from a result of executing the instruction instance, and checking the first residue against the second residue to determine whether errors were introduced while the instruction instance was resident in the execution pipeline.

Abstract: Order indication logic can be recycled for at least two different data hazards, thus reducing the amount of processor real estate consumed by data hazard resolution logic. The logic also allows a single priority picker to be utilized for coloring without the cost of additional pipeline stages. A single priority picker can be utilized to identify memory operations for performing RAW bypass and for resolving OERs. For instance, a data hazard resolution unit resolves at least two different data hazards between resident memory operations and incoming memory operations with a set of logic that indicates order of the resident memory operations relative to the incoming memory operations. The indicated order corresponds to the data hazard being resolved. The data hazard resolution unit includes a priority picker to select one of the indicated resident memory operations for either data hazard.

Abstract: A method and system for performing diagnostic testing to speed the computer boot process. A boot process is initiated and an error counter value is read in any of memory, input/output, central processing, networking, mass storage, or other computing subsystems. The error counter values are compared to subsystem error thresholds. The method includes identifying subsets of subsystems with error counters exceeding error thresholds and then, performing diagnostic tests only on this subset of subsystems as part of the boot process. The error counter may be a correctable error counter that is incremented by an operating system error handler as it isolates subsystem errors. The method includes identifying subsystems in service less than a predefined time threshold by comparing a value stored in a power-on hours field in each subsystem to time thresholds, and including these modules in the tested subset.

Abstract: A system includes a cluster having a plurality of nodes wherein at least one of the nodes is a candidate node, a plurality of resource groups, a clustering mechanism executing on the cluster configured to activate a first resource group of the plurality of resource groups on the candidate node, and a resource group affinity of the plurality of resource groups, wherein the resource group affinity comprises a unidirectional association between the first resource group of the plurality of resource groups and a second resource group of the plurality of resource groups.

Abstract: A duty cycle bounding circuit for restoring the unbounded duty cycle of a periodic signal such as a forwarded clock signal. The duty cycle bounding circuit comprises a state holding logic element, such as a C-element, and a delay line. The delay line feeds back an inverted version of the output of the state holding logic element to an input of the state holding logic element. The periodic signal is applied to another input of the state holding logic element.

Abstract: A soft error recoverable storage element suitable for use in latches, flip-flops, static ram memory cells and microprocessor pipeline stages. The storage element employs a redundant copy of the stored data value and a feedback loop. One embodiment employs an interlocking four inverter loop with gating devices that blocks the propagation of a soft error induced change of state and causes the storage element to recover its original stored data state.

Abstract: A method for predicting and preventing uncorrectable errors that may occur while accessing memory in a computer system. The method involves detecting two or more correctable errors from two or more different physical addresses on each of two or more different bit positions from the same DIMM within a specified period of time, with all of the correctable errors occurring within the same checkword. The method also involves detecting two or more correctable errors from two or more different physical addresses on each of three or more different outputs from the same DRAM within a specified period of time, as long as the three outputs do not all correspond to the same relative bit position in their respective checkwords. This allows a computer system which encounters correctable errors to continue to reliably operate without the unnecessary replacement of functioning memory systems.

Abstract: A method for initializing a module that includes identifying a first module for initialization, and performing a plurality of processing phases on the first module and all modules in a dependency graph of the first module. Performing the plurality of processing phases includes, for each module, executing a processing phase of the plurality of processing phases on the module, determining whether the processing phase has been executed on all modules in a dependency graph of the module, and when the processing phase has been executed for all modules in the dependency graph of the module, executing a subsequent processing phase of the plurality of processing phases on the module.

Abstract: A constrained random test bench methodology employing an instruction abstraction layer. The instruction abstraction layer includes an instruction streamer for generating random test instruction sequences that preserve instruction order dependencies and randomly selecting data values from a valid range of data values. Multiple instruction streamers may be employed to simulate interrupt handlers and other functional design units sharing a control command bus. A priority scheduler sequences the instruction sequences generated by multiple instruction streamers based on a specified priority scheme.

Abstract: The present invention provides systems and method methods for routing packet along redundant, independent paths. The routing is performed based on the destination node for the packets. In certain embodiments the method performs a different routing scheme based on the parity of a globally unique identifier (GUID) of the destination node.

Abstract: A method and system for enabling multi-subprocess handling on computer systems that employ a global process. A virtual memory separator is provided as part of an operating system to interface with a master process and a kernel of the operating system. The separator maps user-specific processes to virtual address spaces that mirror that of the global process. These user-specific processes are empty spaces, excepting their interface—which is identical to that of the global process—and instructions necessary to carry out user-specific processing. When user-specific operations are encountered in the global process, execution is transferred to a respective user-specific process. Since each user-specific process shares addresses and interfaces with the global process, data can be exchanged between them without serialization, which reduces processing overhead.

Abstract: A tape has a component of magnetization pointing out of a plane of the tape. To write a pulse of a servo pattern to the tape, the tape is passed over a write head with a conventional write gap. Current having a fixed polarity is provided to the write head. Once the current achieves a desired value, the current is no longer provided to the write head.

Abstract: In accordance with the invention, a data storage system for fixed content includes one or more peer node computer systems interconnected by a storage system network, where each peer node computer system includes a symmetric storage system application and locally attached storage. A data object is distributively stored on one or more of the one or more peer node computer systems and identified using a unique object identifier. A data object is flexibly stored on the data storage system according to external criteria. Stored data objects are accessible from any of the one or more peer node computer systems. Applications can be executed on the data storage system using data objects that are stored on, being written to, or being read from the data storage system to generate results accessible by a user.

Abstract: A hard disk drive bracket includes a bezel, a lever arm attached to the bezel rotatably between a closed position against the bezel and an open position apart from the bezel, wherein a hard disk drive is locked into the hard disk drive bracket when the lever arm is in the closed position, and a multifunction wireform, wherein the multifunction wireform latches the lever arm in the closed position and releases the lever arm into the open position. The hard disk drive bracket may include a release button, wherein the multifunction wireform releases the lever arm upon pressing of the release button. The multifunction wireform may hold and bias the release button.

Abstract: A movable data center is disclosed that comprises a portable container in which an operable computer system is assembled. A data link, power supply link and cooling system are provided through ports on the exterior of the container. The computer system is assembled to a rack that is secured to the container with a shock absorbing mechanism.

Abstract: A method of determining an organization's network identity capability. The organization's relationships with its employees, customers and business partners, and the organization's technological infrastructure, are examined. By examining the organization's use of identity data (e.g., data identifying customers, employees), the organization's management of that data, and the technology infrastructure can be redesigned to enable better network identity capability. Improved network identity capability enables users' access to multiple applications or services through a single authentication process (e.g., a single login or sign-on), device-independent access to those applications and services, greater protection for the data, improved business processes and collaborations with business partners, etc.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention provide a memory instruction manager for managing the execution of instructions associated with a program. The memory instruction manager assigns a first group identifier to a first instruction associated with a program and to a second instruction associated with the program, and provides, after the first instruction, a memory barrier instruction having the first group identifier such that one or more processors with access to the program are inhibited from executing the second memory instruction until the first memory instruction is executed.

Abstract: A method for generating a word sequence for a passcode involves choosing a schema to guide the generation of the word sequence, and transforming the passcode into the word sequence using the schema, wherein the word sequence contains mnemonic structure.