Abstract: Circuitry including a request queue and a bad address handling circuit. The request queue includes an entry for each outstanding load requesting access to a cache. Each request queue entry includes a valid bit, an issue bit and a flush bit. The state of the valid bit indicates whether or not the associated access request should be issued to the cache. The issue bit indicates whether the load access request has been issued to the cache and the flush bit indicates whether the data retrieved from the cache in response to the request should be loaded into a specified register. The bad address handling circuit responds to a replay load request by manipulating the states of the valid or flush bit of the relevant request queue entry to prevent completion of bad consumer load requests. The bad address handling circuit includes a validation circuit and a flush circuit.

Abstract: A method for compressing 3D geometry data that is capable of compressing both regularly tiled and irregularly tiled surfaces is disclosed. In one embodiment, the method comprises examining 3D geometry data to detect the presence of regularly tiled surface portions. The 3D geometry data is then compressed by: (1) encoding any regularly tiled surface portion using a first encoding method, and (2) encoding any irregularly tiled surface portions using a second encoding method, wherein the second encoding method is different from the first encoding method. The first encoding method may encode the regularly tiled surface portions as vertex rasters, while the second method may encode the irregularly tiled surface portions by geometry compression using a generalized triangle mesh.

Abstract: A carriage, provided with a mounting for one or more media devices is slideably mountable in a system unit (for example a computer system unit) such that the carriage may be slid out of an aperture the system unit. The slideable carriage means that the system unit does not need to be opened in order to insert, remove, or replace a media drive. For example, a media drive can be removed from the system unit by sliding the carriage out of the system unit, disconnecting cables from the media drive and the removing the media drive from the carriage. Similarly, a media drive can be installed in the system unit by mounting the media drive in the carriage, connecting cables to the media drive and reinserting the carriage within the system unit. The use of the slideable carriage is particularly useful for rack mountable systems where it is undesirable to have to remove the system unit from the racking system to insert a media drive.

Abstract: A method of processing data in a system including an utility, includes the steps of starting a session, selecting a file on a local drive or by URL, wherein the file includes a name of a business object, uploading the file including the name of a business object to a server, storing data of the file in a database of the utility, performing asynchronous data processing, and downloading and saving a report after the data processing is completed.

Abstract: A system and method for upgrading software application is disclosed. The system provides a profile upgrade utility that generates a profile of desired application upgrades based upon information provided from a user. In operation, a user may provide a description of modules for upgrade, along with any associated components and a description of the module location. Using this information, the system generates a profile of the desired upgrade. The upgrade profile is then converted to a text file and uploaded to an import/export utility that retrieves the requested upgrades.

Abstract: An improved apparatus and method for modular multiplication and exponentiation to achieve efficient computation involved in Montgomery multiplication is provided. Currently employed conventional iteration methods involve carry look-ahead additions. To overcome the time taken by carry look-ahead additions, there is thus provided, in accordance with a preferred embodiment of the present invention, an apparatus and method for separately storing and tracking the sum and the carry of the addition involved in Montgomery multiplication. In such a manner, the present invention achieves fast addition times since they are not dependent on the time to compute the carries. As a result, the iterations are carried out much faster than previously possible. By representing the value A in the Montgomery multiplication algorithm with a redundant notation, the sum and the carry of the addition are separately stored and tracked, thereby avoiding the delays involved in the computation of the carries.

Abstract: A system for automatically encrypting and decrypting data packet sent from a source host to a destination host across a public internetwork. A tunnelling bridge is positioned at each network, and intercepts all packets transmitted to or from its associated network. The tunnelling bridge includes tables indicated pairs of hosts or pairs of networks between which packets should be encrypted. When a packet is transmitted from a first host, the tunnelling bridge of that host's network intercepts the packet, and determines from its header information whether packets from that host that are directed to the specified destination host should be encrypted; or, alternatively, whether packets from the source host's network that are directed to the destination host's network should be encrypted.

Abstract: Methods and apparatus for detecting and reporting memory leaks associated with an operating system are disclosed. In accordance with one aspect of the present invention, a method for identifying a section of dynamically allocated memory which may not be explicitly freed includes processing information associated with a failure of an operating system and identifying a call-site that is associated with the section of the dynamically allocated memory using the information. Once the call-site is identified, a report may be generated to identify the call-site as being associated with the section of dynamically allocated memory. In one embodiment, obtaining information associated with a failure of the operating system includes obtaining an image of the operating system which is created when a kernel associated with the operating system crashes.

Abstract: A method for significantly decreasing the number of times prior art coding schemes, such as variable length coding, are implemented in the course of encoding/decoding a given data block includes cataloging the occurrences, or locations, of a designated frequently occurring value in the data block and then excluding the frequently occurring value from the prior art coding scheme.

Abstract: A memory module with offset notches for improved insertion and a memory module connector for mating thereto. The connector housing includes an accommodating s space for receiving a portion of the memory module printed circuit board (PCB). A first key is disposed within the accommodating space of the housing and is positioned between the first end and the center of the housing. A second key is flirter disposed within the accommodating space and is positioned between the second end of the housing and the center. A distance between the first key and the second key is greater than 40% of the length of the housing. Either the first, second, or both keys may extend from the accommodating space beyond a top plane defined by a top side of the accommodating space of the housing. The memory module comprises the PCB with a first notch positioned between the first end of the PCB and the center of the PCB. A second notch is positioned between the second end of the PCB and the center of the PCB.

Abstract: A method for selecting a candidate to mark as overwritable in the event of a cache miss while attempting to avoid a write back operation. The method includes associating a set of data with the cache access request, each datum of the set is associated with a way, then choosing an invalid way among the set. Where no invalid ways exist among the set, the next step is determining a way that is not most recently used among the set. Next, the method determines whether a shared resource is crowded. When the shared resource is not crowded, the not most recently used way is chosen as the candidate. Where the shared resource is crowded, the next step is to determine whether the not most recently used way differs from an associated source in the memory and where the not most recently used way is the same as an associated source in the memory, the not most recently used way is chosen as the candidate.

Abstract: Three-dimensional compressed geometry is decompressed with a unit having an input FIFO receiving compressed data bits and outputting to an input block state machine and an input block, whose outputs are coupled to a barrel shifter unit. Input block output also is input to Huffman tables that output to the state machine. The state machine output also is coupled to a data path controller whose output is coupled to a tag decoder, and to a normal processor receiving output from the barrel shifter unit. The decompressor unit also includes a position/color processor that receives output from the barrel shifter unit. Outputs from the normal processor and position/color processor are multiplexed to a format converter. For instructions in the data stream that generate output to the format converter, the decompression unit generates a tag sent to the tag decoder in parallel with bits for normals that are sent to the format converter.

Abstract: Three-dimensional compressed geometry is decompressed with a unit having an input FIFO receiving compressed data bits and outputting to an input block state machine and an input block, whose outputs are coupled to a barrel shifter unit. Input block output also is input to Huffman tables that output to the state machine. The state machine output also is coupled to a data path controller whose output is coupled to a tag decoder, and to a normal processor receiving output from the barrel shifter unit. The decompressor unit also includes a position/color processor that receives output from the barrel shifter unit. Outputs from the normal processor and position/color processor are multiplexed to a format converter. For instructions in the data stream that generate output to the format converter, the decompression unit generates a tag sent to the tag decoder in parallel with bits for normals that are sent to the format converter.

Abstract: Methods and apparatus for facilitating a global safepoint operation in a multithreaded computer system are disclosed. According to one aspect of the present invention, each thread keeps track of its safepoint regions by maintaining a variable which indicates a state, such as whether the current region of the thread is safe, unsafe, or transitional. In this manner, it can be determined whether a thread is currently in a safepoint region without suspending the thread. When a thread is currently in a safepoint region, the thread can continue to operate while a global safepoint operation, such as garbage-collection is being performed. When the thread begins to transition out of the safe region, it moves into a transitional region. The transitional region automatically blocks the transition into the non-safe region to assure that the safepoint operation occurs in a safe region.

Abstract: The present invention provides a shared instruction cache for multiple processors. In one embodiment, an apparatus for a microprocessor includes a shared instruction cache for a first processor and a second processor, and a first register index base for the first processor and a second register index base for the second processor. The apparatus also includes a first memory address base for the first processor and a second memory address base for the second processor. This embodiment allows for segmentation of register files and main memory based on which processor is executing a particular instruction (e.g., an instruction that involves a register access and a memory access).

Abstract: A method for assigning power and ground pins in array packages in order to enhance next level routing is provided. In one embodiment, the method comprises arranging connections of a semiconductor array package, the semiconductor package having an integrated circuit with power, ground, and signal connections, in 2×3 connection grids. Each connection grid includes a power connection and a ground connection which is adjacent to the power connection. The 2×3 connection grids are arranged so that each connection at the periphery is a signal connection. A 4:1:1 signal:power:ground connection ratio is maintained in the arrangement, wherein no more than four signal connections are present for each power connection, and no more than four signal connections are present for each ground connection.

Abstract: A microprocessor includes multiple register files. In a single thread mode, the microprocessor allows a single thread to have access to multiple ones of the register files. In a multi-thread mode, each thread has access to respective ones of the register files. In the multi-thread mode, multiple threads are simultaneously executing. Circuitry and hardware are provided to facilitate the respective modes and to facilitate transitions between the modes.

Abstract: Provided is a method, system, and program for managing multiple resources in a system. A user request is received to generate a configuration policy. User selection is received of a set of the multiple resources. A determination is made of at least one element for each selected resource in the set, wherein each element is capable of managing one of the resources in the system. User selection is received of one element for each selected resource in the set. The configuration policy is defined to include the user selected elements, wherein invoking the configuration policy further invokes each element defined in the configuration policy to configure the resources associated with the invoked elements.

Abstract: Using a subtraction without borrow operation, the first operand lowest order word is subtracted from a second operand lowest order word. If the result of the subtracting is not zero, then a zero (Z) flag is cleared such that a Z flag status is not set. If, however, the result of the subtracting is zero, then the Z flag is set as usual. Next, a first operand next higher order word is subtracted from a second operand next higher order word using a subtraction with borrow and a sticky not Z flag (SBBZ) instruction and, based upon the subtracting, the Z flag is updated accordingly such that it represents the result of the whole multi-word subtraction until the first operand highest order word is subtracted from the second operand highest order word. The comparing of the first operand and the second operand is then based upon the Z flag status, if needed, after the subtraction of the first operand highest order word is subtracted from the second operand highest order word.

Abstract: An AC sequencer receives source AC voltage via a sequence-mounted universally accepted connector, such as an IEC 309 compatible connector. Source AC is coupled by an AC connector plug and AC power cord from a wall socket to the AC sequencer via a mating connector. Although specifications for the AC power cord and AC connector will vary from country to country, the same AC sequencer may be used in many countries. Further, the AC sequencer receives control and status signals via sequencer-mounted universally accepted connectors, and can respond to signals that may be voltage-sourced, current-sourced, in addition to signals representing switch openings and closures. This permits a master server AC sequencer to be intelligently daisy-chained to remote slave units containing a similar AC sequencer, such that status information may be received from and control signals sent to the slave unit.