Abstract: A coprocessor coupled to a hardware processor and capable of performing multimedia operations is provided. The coprocessor includes an instruction fetch and decode unit which is coupled to a plurality of execution units including an integer execution unit and a multimedia execution unit. The coprocessor includes a superscalar architecture and each of the execution units includes a plurality of pipelined stages. Accordingly, the multimedia execution unit has several integer execution units which can be executed in parallel for improved multimedia performance. A visible register set is coupled to the integer execution unit for receiving operands to initialize operation of the coprocessor. Further, a first register file is coupled to the multimedia execution unit and a second register file is coupled to the integer execution unit. A memory bus coupled to memory and the integer execution unit is used for accessing data and multimedia applications in memory as indicated by values in the visible register set.

Abstract: A symmetrical multiprocessing system includes a plurality of nodes interconnected by a hierarchical bus. To allow for the transfer of data between nodes and to restrict the global transfer of local transactions, a plurality of address partitions are defined: global space, local space, remote read space, and remote read and write space. Process private and local data is accessed using local space. Global data is accessed using global space. In one embodiment, a kernel of the operating system is resident in the local space of each node. Because the memory space where the kernel resides is designated as local space, no other nodes can write to, or corrupt, the node's kernel.

Abstract: The present invention describes a method and system for managing high-availability-aware components in a networked computer system. In particular, the method includes registering components and dynamically allocating roles and assignments to one or more of the registered components to achieve a desired level of redundancy based on component type information. The method may include an additional step of performing administrative actions on the registered components in response to a request from an external management agent in order to increase the availability of services provided by the high-availability-aware components. Further, the method may additionally include responding to an error by changing roles and assignments of one or more of the registered components, providing information to registered components so that related components may communicate to achieve a desired redundancy level, and/or maintaining additional information relevant to managing high-availability-aware components.

Abstract: Methods and apparatus for enabling inconsistent or unsafe threads to efficiently reach a consistent or safe state when a requesting thread requests a consistent state are disclosed. According to one aspect of the present invention, a method for requesting a consistent state in a multi-threaded computing environment using a first thread includes acquiring a consistent state lock using the first thread, and identifying substantially all threads in the environment that are inconsistent. The state of the inconsistent threads is altered to a consistent state, and the first thread is notified when the states of the previously inconsistent threads have been altered to be consistent. Once the first thread is notified, the first thread releases the consistent state lock. In one embodiment, the method also includes performing a garbage collection after releasing the consistent state lock using the first thread.

Abstract: A computer system optimized for block copy operations is provided. In order to perform a block copy from a remote source block to a local destination block, a processor within a local node of the computer system performs a specially coded write operation. The local node, upon detection of the specially coded write operation, performs a read operation to the source block in the remote node. Concurrently, the write operation is allowed to complete in the local node such that the processor may proceed with subsequent computing tasks while the local node completes the copy operation. The read from the remote node and subsequent storage of the data in the local node is completed by the local node, not by the processor. In one specific embodiment, the specially coded write operation is indicated using certain most significant bits of the address of the write operation.

Abstract: A digital data processing apparatus has a primary data storage element that stores data for access by one or more processes, as well as a secondary data storage element, e.g., a disk drive, for non-volatile data storage. A paging mechanism selectively transfers sets of data between the primary data storage element and an associated data file on the secondary data storage element. A directory stores “atomic” signals, or bits, each reflecting a state of one or more subsets of data in respective sets. The paging mechanism includes a page-out element that stores data from a subset of a set to the associated data file. During paging, the page-out element responds to data in the subset which are associated with the atomic state (as indicated by the atomic bit) for storing to an associated status file on the secondary data storage element attributes of the paged data. Those signals can be, for example, the atomic bits themselves.

Abstract: A power sub-frame is provided for a system unit. The power sub-frame has four walls defining first, second, third and fourth sides of a open, rectangular frame. A fifth side is open for receiving a plurality of power supply units for powering the system unit. A power distribution board located at a sixth side of the frame opposite to the open side, for making electrical contact to the power supply units. The power sub-frame can be manufactured as a sub-assembly for the system unit, facilitating manufacture, testing and maintenance. The power sub-frame can be pre-assembled with power distribution logic and cabling ready to be mounted in a system unit. The system unit can, for example, be a computer system unit for rack mounting in a telecommunications application.

Abstract: A multiprocessing computer system includes a plurality of nodes interconnected through a global interconnect network which supports cluster communications. An initiating node may launch a request to a remote node's memory. A remote cluster node may be reached by passing the request through one or more intermediate nodes configured in pass-through mode. Accordingly, various global network topologies may be supported. The pass-through mode may be advantageously accommodated using a node having hardware which is similar to other nodes in the system. More particularly, the pass through mechanism may be implemented without significantly altering a node's local bus transactions. In one specific implementation, when the system interface of a particular node receives a transaction, the address of the transaction is checked to determine if the transaction should be treated as a pass through transaction.

Abstract: A program loading arrangement is used in connection with a virtual machine for loading programs for processing in the virtual machine. The program loading arrangement includes a program/class loader and a dependency list. The dependency list identifies, for each program for which one or more classes are to be instantiated in the virtual machine for use during processing of the respective program, the class or classes that are to be so instanitated. In response to a request to load a program for processing in the virtual machine, the program/class loader initiates loading of the program. In addition, the program/class loader determines from the dependency list whether any classes are to be instantiated for use during processing of the program being loaded and, if so, instantiates the respective classes.

Abstract: Three-dimensional compressed geometry is decompressed with a unit having an input FIFO receiving compressed data bits and outputting to an input block state machine and an input block, whose outputs are coupled to a barrel shifter unit. Input block output also is input to Huffman tables that output to the state machine. The state machine output also is coupled to a data path controller whose output is coupled to a tag decoder, and to a normal processor receiving output from the barrel shifter unit. The decompressor unit also includes a position/color processor that receives output from the barrel shifter unit. Outputs from the normal processor and position/color processor are multiplexed to a format converter. For instructions in the data stream that generate output to the format converter, the decompression unit generates a tag sent to the tag decoder in parallel with bits for normals that are sent to the format converter.

Abstract: A computer system optimized for block copy operations is provided. In order to perform a block copy from a remote source block to a local destination block, a processor within a local node of the computer system performs a specially coded write operation. The local node, upon detection of the specially coded write operation, performs a read operation to the source block in the remote node. Concurrently, the write operation is allowed to complete in the local node such that the processor may proceed with subsequent computing tasks while the local node completes the copy operation. The read from the remote node and subsequent storage of the data in the local node is completed by the local node, not by the processor. In one specific embodiment, the specially coded write operation is indicated using certain most significant bits of the address of the write operation.

Abstract: A memory has memory cells arranged in rows and columns. The memory cells of each row are coupled to a word line that is separate from word lines connecting to the memory cells of other rows. Each column has mutually exclusive subsets of memory cells. The memory cells are coupled to bit lines. Each bit line is coupled to a selected mutually exclusive subset of memory cells. The memory cells of a selected row output a cell voltage on the coupled bit lines when the coupled word line is asserted. A multiplexor receives the cell voltages on the bit lines. The multiplexor is responsive to column select signals to select one of the columns as a selected column, and outputs a multiplexor voltage corresponding to the cell voltage of the memory cell of the selected row and the selected column.

Abstract: A handheld computing device is used to copy files from the screen of a fixed computer. The display of the handheld device is linked to that of the underlying computer and file and directory icons together with their underlying files are copied to the handheld device. Files from the handheld device can also be transferred to the fixed computer. When a user is running a program on the fixed computer, he may capture the state of that computer and transfer everything needed to permit execution of that program to continue uninterrupted on the handheld device. Thus files and executing programs may be lifted from the fixed computer and used on the handheld device.

Abstract: Apparatus, methods and computer program products permit a decision to record time sequential information, beginning at a particular point in time, to be made after that particular point in time. In one implementation, a decision to record a piece of music from the beginning can be made anytime during the playing of the music. In others, a decision to record a video program from the beginning can be made during the program. In a portable video camera, a decision to save a boy's turn at bat can be made after he hits a home run.

Abstract: A data processing system comprises a plurality of nodes an-d a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a memory which is partitioned into a plurality of sections, including a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory. A local bus connects the processor, block sharable memory and printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board.

Abstract: A method and apparatus for secure and scalable key management in a multicast network environment is provided. In a first portion, one or more seed nodes on the network receive a multicast transmission request for a cryptographic key from a requesting node. The seed node compares the identity of the requesting node with an authenticated predetermined list of nodes having permission to receive the cryptographic key. If the comparison indicates the requesting node is not a member of the authenticated predetermined list, the seed node denies the multicast request. However, if the comparison indicates that the requesting node is a member of the predetermined list of nodes, the cryptographic key is transmitted using a secure unicast key distribution technique such as SKIP. A second portion concerns the requesting node which generates a multicast request to obtain the cryptographic key from one or more seed nodes and one or more keyed nodes on the internetwork.

Abstract: A method and system for storing data in a hash table of a computer system. A hash function specifies a storage location of the hash table for data associated with a given key. But instead of storing the key in this location, a smaller value, denoted a specification value is used. Specification values are produced via a specification function that mathematically captures the information lost by the hashing function when the key is mapped to the hash address. As a result, no two keys can have equal specification values and equal hash values. When examining the data stored at any given hash address, the invention recreates the key's specification value and compares it with the stored specification value. When the compared values are equal, the object is identified. Thus, the invention conclusively establishes whether the data is associated with a given key without storing the key in the hash table.

Abstract: A high speed self-terminated output driver includes an array of resistive drivers that are pulse-activated in succession to process a corresponding succession of data bits. The output driver thus synthesizes an output waveform which behaves similar to a single resistive drive element responding to the non-bandlimited input signal. In various embodiment, the output driver provides for digitally programmable output impedance and pre-distortion levels.

Abstract: A multiprocessor digital data processing system comprises a plurality of processing cells arranged in a hierarchy of rings. The system selectively allocates storage and moves exclusive data copies from cell to cell in response to access requests generated by the cells. Routing elements are employed to selectively broadcast data access requests, updates and transfers on the rings.