Abstract: A torque wrench having an indicator may be used to apply a desired amount of torque to a fastener to secure together two printed circuit boards within an electronic system. The torque wrench includes a handle and a drive head. The handle may include a lever arm, a looped section, and a drive section. A gap is formed between a portion of the lever arm and a portion of the drive section. When force is applied to the handle to tighten a fastener, the force causes the gap to narrow. A desired amount of torque is applied to the fastener by the torque wrench when the gap between the portion of the lever arm and the portion of the drive section closes. The torque wrench is storable within an enclosure of the electronic system when not in use to tighten a fastener.

Abstract: A remote terminal emulator (RTE) is provided in which substantially all of the time elapsing during an emulated use of a computer system under test is categorized and reported. The time required by the computer system under test to respond to command signals transmitted by the RTE is recorded as a receive time and is measured from completion of the transmission of the command signals to recognition of a pattern specified by the RTE as signifying completion of the response by the computer system under test. As a result, the receive time recorded reflects the time required by the computer system under test to (a) process and carry out the command transmitted by the RTE and (b) transmit response data back to the RTE.

Abstract: A memory module with offset notches for improved insertion and a memory module connector for mating thereto. The connector housing includes an accommodating space for receiving a portion of the memory module printed circuit board (PCB). A first key is disposed within the accommodating space of the housing and is positioned between the first end and the center of the housing. A second key is further disposed within the accommodating space and is positioned between the second end of the housing and the center. A distance between the first key and the second key is greater than 40% of the length of the housing for stability of the memory module while encased by the housing. Either the first, second, or both keys may extend from the accommodating space beyond a top plane defined by a top side of the accommodating space of the housing. The memory module comprises the PCB with a first notch positioned between the first end of the PCB and the center of the PCB.

Abstract: A central processing unit of a computer includes a single-ported data cache and a dual-ported prefetch cache. The data cache accommodates a first pipeline and the prefetch cache, which is much smaller than the data cache, accommodates both the first pipeline and a second pipeline. If a data cache miss occurs, a row of data corresponding to the specified address is stored in the data cache and the prefetch cache. Thereafter, if a prefetch cache hit occurs, a row of data corresponding to a prefetch address is loaded into the prefetch cache. The prefetch address may, for instance, be generated by adding a fixed increment to the specified address. This operation frequently results in the prefetch cache storing data soon requested by a computer program. When this condition is achieved, the data corresponding to the subsequent address request is rapidly retrieved from cache memory without incurring memory latencies associated with the external cache, the primary memory, and the secondary memory.

Abstract: A method, apparatus and computer program product for a non-atomic (i.e., user controllable) format converter that affords a user the ability to control the structure of the converted document as well as selectively add information to or otherwise modify selected portions of the converted document is described.

Abstract: A method for estimating rendering times for three-dimensional graphics objects and scenes is disclosed. The rendering times may be estimated in real-time, thus allowing a graphics system to alter rendering parameters (such as level of detail and number of samples per pixel) to maintain a predetermined minimum frame rate. Part of the estimation may be performed offline to reduce the time required to perform the final estimation. The method may also detect whether the objects being rendered are pixel fill limited or polygon overhead limited. This information may allow the graphics system to make more intelligent choices as to which rendering parameters should be changed to achieve the desired minimum frame rate. A software program configured to efficiently estimate rendering times is also disclosed.

Abstract: A heat sink for cooling a high power consumption device, such as a central processing unit (device), has extended heat transfer areas. In an embodiment, the extended heat transfer areas may include fins protruding from portions of a heat sink base. The extended heat transfer area of the heat sink may overhang an area of a circuit board adjacent to the high power consumption device. Low power consumption components, such as memory chips, can be mounted on the circuit board in close proximity to the high power consumption device and beneath the heat sink. The low power consumption component may have separate heat sinks that attach to the low power consumption components and extend beyond the base of the high power consumption device heat sink.

Abstract: A microprocessor with reduced context switching overhead and a corresponding method is disclosed. The microprocessor comprises a working register file that comprises dirty bit registers and working registers. The working registers including one or more corresponding working registers for each of the dirty bit registers. The microprocessor also comprises a decoder unit that is configured to decode an instruction that has a dirty bit register field specifying a selected dirty bit register of the dirty bit registers. The decoder unit is configured to generate decode signals in response. Furthermore, the working register file is configured to cause the selected dirty bit register to store a new dirty bit in response to the decode signals. The new dirty bit indicates that each operand stored by the one or more corresponding working registers is inactive and no longer needs to be saved to memory if a new context switch occurs.

Abstract: A CMOS impedance matching circuit includes an amplifier and a feedback circuit. The amplifier allows control of the impedance by controlling the V/I characteristic. The amplifier is sized to provide the desired impedance. The feedback circuit clamps the maximum excursions of the input signal, thereby maximizing signal speed. It also provides a higher impedance to noise beyond the dead band. In one embodiment of the present invention, the amplifier includes an amplifier circuit in parallel with an amplifier buffer. The amplifier buffer provides no gain and simply performs the inverting function when no gain is required for impedance matching. In one embodiment, the amplifier circuit includes a plurality of switchable amplifiers coupled in parallel with each other. Each of the switchable amplifiers has a different gain, and the one with the right amount of gain for the needed impedance matching is chosen using control inputs.

Abstract: A system for accessing control and status registers for a device within a computer system. These control and status registers are used to control and configure the device and to read status information from the device. The system operates by serially shifting an index into an index register within the device. This index specifies a target register to be accessed within the control and status registers. During a write operation to the target register, the system serially shifts a data value into a data register within the device, and then moves the data value from the data register into the target register. During a read operation from the target register, the system loads a value into the data register from the target register, and serially shifts the value from the data register to a location outside the device to complete the read operation.

Abstract: In accordance with the present invention a process is provided for allocating and deallocating resources in a distributed processing system having a requester platform and a server platform. The process involves receiving a request from the requestor platform referring to a system resource and specifying a requested lease period, permitting shared access to the system resource for a lease period, sending a return call to the requestor platform advising of the lease period, and deallocating the system resource when the lease period expires.

Abstract: The present invention provides an efficient method for fetching instructions having a non-power of two size. In one embodiment, a method for fetching instructions having a non-power of two size includes fetching a first instruction cache line having a power of two size for storage in a first line buffer of an instruction fetch unit of a microprocessor, fetching a second instruction cache line having a power of two size for storage in a second line buffer of the instruction fetch unit, and extracting and aligning instruction data stored in the first line buffer and the second line buffer to provide an instruction having a non-power of two size.

Abstract: An object structure's header (40) allocates a two-bit synchronization-state field (42) solely to monitor data for implementing synchronization on that object. When the object is locked by a particular execution thread, or when one or more execution threads are waiting for a lock or notification on that object, its header contains a pointer to monitor resources in the form of a linked list of lock records (50, 52, 54) associated with the threads involved. The synchronization-state field (42) ordinarily contains an indication of whether such a linked list exists and, if so, whether its first member is associated with a thread that has a lock on the object. When a thread attempts to gain access to that linked list, it employs an atomic swap operation to place a special busy value in that lock-state field (42) and write its execution-environment pointer into the object's header (40).

Abstract: The claimed invention can be used to automatically determine what files are needed to optimally execute a computer program to a desired state. In one embodiment the invention automatically creates an optimized file containing the files that are necessary to reach the desired state of a computer program. One or more remainder files may also be created. A remainder file contains the files that may be used by the computer program after reaching the desired state of execution.

Abstract: A computer system optimized for block copy operations is provided. In order to perform a block copy from a remote source block to a local destination block, a processor within a local node of the computer system performs a specially coded write operation. The local node, upon detection of the specially coded write operation, performs a read operation to the source block in the remote node. Concurrently, the write operation is allowed to complete in the local node such that the processor may proceed with subsequent computing tasks while the local node completes the copy operation. The read from the remote node and subsequent storage of the data in the local node is completed by the local node, not by the processor. In one specific embodiment, the specially coded write operation is indicated using certain most significant bits of the address of the write operation.

Abstract: The present invention comprises a method and apparatus for receiving data analysis instructions from a user and for displaying results of the data analysis to the user. In one embodiment, the invention provides a series of interface windows displayed on a computer display screen. A first window allows a user to select one or more specification files comprising reference data specifying capabilities and or resources with which other data is to be compared. A second window allows the user to select one or more data files to be compared to the one or more specification files selected using the first window. A third window allows the user to interactively select the type of analysis to be performed and provides the results of the selected analysis to the user.

Abstract: A method and apparatus for authenticating users. Prior art mechanisms require each individual application (running on an “application server”) that the user is accessing to provide for the ability to use the various authentication mechanisms. One or more embodiments of the invention externalize the authentication mechanism from the application in the form of a login server. Only the login server needs to be configured to handle authentication mechanisms. The application server checks if a request has an active and valid session (e.g., a valid session may exist when there is active communication between a client and server that has not expired). If there is not a valid session, the application server redirects the user to the login server. The login server attempts to authenticate the user using any desired authentication mechanism. Once authenticated, the login server redirects the user back to the application server.

Abstract: A system and method of reducing wire-or glitch to improve bus speeds. In a system that supports wire-or functions, the rise time of the wave created by the off-going driver is controlled. The off-going wave is forced to climb gradually such that one propagation delay of the loaded bus later, it is only marginally above a high threshold voltage. The fall time of the wave created by an on-going driver is minimized such that a strong negative going voltage propagates down the bus. This strong negative going voltage drags a composite wave on the bus (i.e. the combination of the waves of the on-going driver and the off-going driver) back below a low threshold voltage approximately one propagation delay after the switching occurs.

Abstract: Methods and apparatus for element selection exhausting an entire array are disclosed. A method for processing an array having a plurality of elements includes selecting one of the plurality of elements. An index is maintained dividing the array into a first section containing each selected one of the plurality of elements and a second section containing each unselected one of the plurality of elements. The selected one of the plurality of elements is then swapped with an unprocessed element in the array such that the selected one of the plurality of elements is stored in the first section of the array. The selected one of the plurality of elements may then be processed.

Abstract: A method for determining the setup and hold times of static flip-flops during the design and development of integrated circuits. The method utilizes simulations of an integrated circuit to determine a first amount of time required for a data signal to be transmitted from a first external node to a predetermined node in the register of a static flip-flop, and a second amount of time required for a clock signal to be transmitted from a second external node to the predetermined node. The setup time is determined by calculating a difference between the first amount of time from the second amount of time. Similarly, a hold time for the flip-flop is determined by calculating a difference between the amounts of time required for data and the clock signal to reach a second predetermined internal node of the flip-flop.