Abstract: A bus bridge for a computer system for bridging first and second buses includes a shift and accumulate unit. The shift and accumulate unit includes a shifter having an input connected to receive bytes from one of the first and second buses and an output providing a selectable shift to the received bytes. The shift and accumulate unit also includes an accumulator having an input connected to receive the output of the shifter and providing accumulation of selectable bits of the shifted bytes, the accumulator having an output for supplying realigned bytes to be passed to the other of the first and second buses. The combination of the shifter and the accumulator permits a desired amount of shift to be combined with the accumulation of selected bits or bytes to realign sets of bytes from one bus and to form sets of bytes for the other bus. Burst transfer is also possible by operating the shift and accumulate unit to operate in successive cycles for successive sets of input bytes from one of the buses.

Abstract: An instruction fetch unit for fetching instructions from an instruction cache of a processor. The fetch unit includes a next fetch address mechanism generating predicted next fetch addresses, the next fetch address mechanism generating a next fetch address for a fetch bundle over at least two cycles of the processor. The next fetch address mechanism determines the next fetch address based on whether a control transfer instruction from an intermediate set of fetched instructions is taken.

Abstract: A JMS provider first applies any specified JMS selector to determine if the message is to be sent to the topic subscriber. If the answer is yes, the JMS provider under this invention checks if the message is an XML message. If it is an XML message, and it conform to the specified XML schema it is transformed using the specified filter and an XSLT engine. The resulting modified XML document is sent to the topic subscriber. In the case that it is an XML message but one that conforms to a different schema than the one specified with the filter, then the XML message is sent without any transformation to the topic subscriber.

Abstract: A graphics system comprises a texture memory, a rendering engine, a sample buffer and a filtering engine. The rendering engine renders received primitives based on a render pixel array whose vertical and horizontal resolutions are dynamically programmable. The rendering engine determines render pixels that geometrically intersect a primitive. For each intersecting render pixel, a texture access may be required (if texture processing is turned on) to determine texture values. The texture values may be used to compute sample values at sample positions interior to the sample render pixel and the primitive. A controlling agent may decrease the vertical and horizontal resolutions of the render pixel array to control frame render time. The filtering engine may programmably generate virtual pixel centers covering the render pixel array. Any change in the render pixel resolutions may require an accommodating change in the virtual pixel array parameters.

Abstract: In a client-server environment it would be desirable to have a number of servers capable of processing a broad range of applications such as compute intensive applications or graphic operations such as rendering. In a heterogeneous client-server environment, conventional systems statically stored executables on a server for later execution. This required extensive storage as well as many programmer hours porting applications to the server machine from client machines which had different object modules. This invention solves these problems by creating a homogeneous execution environment within a heterogenous client-server network. Accordingly, this system dynamically downloads code on a compute server, executes the code on the compute server, and returns the results to the calling client method. This technique does not require multiple copies of code to be downloaded nor compiled since the server code can be executed on all the different systems.

Abstract: A method and apparatus for modeling the specular reflection of light from an object is disclosed. In accordance with one embodiment of the method, a portion of the object is modeled by one or more surfaces each having at least one vertex and an edge point corresponding to an edge. A sine value associated with a highlight angle is determined at each vertex and edge point, and a control value is determined at each vertex and edge point using the sine values. A specular input component at each point on the surface is determined using the control values. The specular input component is utilized to determine the specular light component at that particular point. Embodiments of apparatus implementing the method are also disclosed.

Abstract: A method is provided for load balancing requests for an application among a plurality of instances of the application operating on a plurality of servers. A policy is selected for choosing a preferred server from the plurality of servers according to a specified status or operational characteristic of the application instances, such as the least-loaded instance or the instance with the fastest response time. The policy is encapsulated within multiple levels of objects or modules that are distributed among the servers offering the application and a central server that receives requests for the application. A first type of object, a status object, gathers or retrieves application-specific information concerning the specified status or operational characteristic of an instance of the application. Status objects interact with instances of the load-balanced application and are configured to store their collected information for retrieval by individual server monitor objects.

Abstract: In accordance with the present invention a process is provided for allocating and deallocating resources in a distributed processing system having a requester platform and a server platform. The process involves receiving a request from the requestor platform referring to a system resource and specifying a requested lease period, permitting shared access to the system resource for a lease period, sending a return call to the requestor platform advising of the lease period, and deallocating the system resource when the lease period expires.

Abstract: A system is disclosed for performing floating point computation in connection with numbers in a base floating point representation (such as the representation defined in IEEE Std. 754) that defines a plurality of formats, including a normalized format and a de-normalized format, using a common floating point representation that defines a unitary normalized format. The system includes a base to common representation converter, a processor and a common to base representation converter. The base to common representation converter converts numbers from the base floating point representation to the common floating point representation, so that all numbers involved in a computation will be expressed in the unitary normalized format. The processor is configured to perform a mathematical operation of at least one predetermined type in connection with the converted numbers generated by the base to common representation converter to generate a floating point result in the common representation.

Abstract: A method and apparatus for finding bugs related to garbage collection in a virtual machine. For each possible garbage collection point in a stream of execution, a compiler in the virtual machine provides a map that specifies live pointer locations in the stack. In addition, the map identifies those locations in the stack that contain other forms of live data, such as integers. All other locations are considered “dead,” i.e., no longer in use or never used. At each garbage collection point, “dead” locations in the stack are overwritten with an invalid pointer value. Because of the overwriting process, any bug in the compiler that causes a live pointer to be omitted from the map also causes the omitted pointer to be overwritten with the invalid pointer value.

Abstract: A method for routing conductive paths in an integrated circuit, each conductive path having a first pin and a second pin is described herein. The method includes separating at least two conductive paths into groups based on the connection type of each of said conductive paths, the connection type for a given conductive path being determined based on the types of pins at each end of the conductive path, ranking each group based upon how constrained each connection type is relative to each other connection type, choosing the group having the most constrained connection type which has not yet been routed, and routing each conductive path within the group chosen during the choosing operation.

Abstract: A multiprocessor computer system which provides fault tolerance includes a number of processing sets. At least one of the processing sets is operable asynchronously of a second processing set. A monitor is connected to receive I/O operations output from the processing sets for identifying faulty operation of those units. The monitor is also operable to synchronise operation of the processing sets by signalling the processing sets on receipt of outputs from those units indicative of a plurality of them being at an equivalent stage of processing. The monitor provides for buffering of I/O operations output from the processing sets and for selective forwarding of those I/O operations to an external I/O bus. The processing set may be formed from a single processor or from multiple processors.

Abstract: The Hat Trick deque requires only a single DCAS for most pushes and pops. The left and right ends do not interfere with each other until there is one or fewer items in the queue, and then a DCAS adjudicates between competing pops. By choosing a granularity greater than a single node, the user can amortize the costs of adding additional storage over multiple push (and pop) operations that employ the added storage. A suitable removal strategy can provide similar amortization advantages. The technique of leaving spare nodes linked in the structure allows an indefinite number of pushes and pops at a given deque end to proceed without the need to invoke memory allocation or reclamation so long as the difference between the number of pushes and the number of pops remains within given bounds. Both garbage collection dependent and explicit reclamation implementations are described.

Abstract: A digital data processing apparatus has a memory element that stores data for access by one or more processes, as well as a secondary storage element, e.g., a disk drive, for non-volatile data storage. A paging mechanism selectively transfers sets of data between the memory and an associated data file on the disk. A directory stores signals reflecting an attribute of one or more data in the set. The paging mechanism includes a page-out element that stores data from a subset of the set to the associated data file. During paging, that element responds to data in the subset which are associated with the attribute—as reflected by the directory—for storing to an associated status file on the disk that attribute.

Abstract: A method and apparatus for switching between threads of a program in response to a long-latency event. In one embodiment, the long-latency events are load or store operations which trigger a thread switch if there is a miss in the level 2 cache. In addition to providing separate groups of registers for multiple threads, a group of program address registers pointing to different threads are provided. A switching mechanism switches between the program address registers in response to the long-latency events.

Abstract: A method and system for providing an executable module having an address space for storing program data that is to reside in a read-only storage medium and an address space for storing program data that is to reside in a random access memory is herein described. The executable module represents Java classes that are structured for dynamic class loading. A static class loader is used to modify the class structure to accommodate static loading. The static class loader also identifies methods that contain unresolved symbolic references and data that varies during the execution of the module. These methods and data are identified in order to place them in the address space that resides in the random access memory. The static loader is beneficial in a distributed computing environment having a client computer that has little or no secondary storage thereby requiring applications to run entirely in random access memory.

Abstract: An information handling system includes a plurality of transmission lines coupled together at one end and having a characteristic impedance, a driver circuit coupled to one of the transmission lines, a plurality of receiver circuits individually coupled to distinct ones of the transmission lines for resolving the signals, and on-chip terminators having a output impedance corresponding to the characteristic impedance and that can be coupled or decoupled from a node by on-chip circuitry. In this embodiment, the terminators are separate and distinct from driver circuitry. However, when a node is in a receive configuration, its corresponding termination resistor is tied to the transmission line at that node, and its corresponding driver circuit presents a high impedance output to the node.

Abstract: The present invention relates to a method and circuit for prefetching direct memory access descriptors from memory of a computer system, and storing the prefetched direct memory access descriptors within a unified descriptor memory for subsequent access by direct memory access controllers. The descriptors are generated by a central processing unit of the computer system while executing software applications. The descriptors define data transfer operations between memory of the computer system and input/output devices via direct memory access controllers. The direct memory access controllers generate requests for descriptors. Upon generation of a request, the unified descriptor memory is checked to determine whether the requested descriptor is contained therein. If the requested descriptor is contained within the unified descriptor memory, the request descriptor is provided to the requesting direct memory access controller.

Abstract: A turnstile FIFO stores data packet from each of a number of separate ordered sets in a generally circular list structure. A select data packet can be dequeued if no older data packet of the same ordered set is stored in the turnstile FIFO. The data packets are stored in the turnstile FIFO in a globally sequential order such that older data packets precede younger data packets regardless of membership in the one or more ordered sets. Turnstile logic determines whether the selected data packet is the oldest data packet of a given ordered set by determining set membership of all older data packets stored in the turnstile FIFO. Older data packets are stored in positions within the turnstile FIFO which precede the position of the selected data packet.

Abstract: One embodiment of the invention provide for access and use of information from fonts in multiple formats (including font format specific information) in an object oriented system. A generic private Font Handler abstract class is defined with multiple methods and references to objects and variables to provide for the storage and retrieval of information. Subclasses of the Font Handler class implement the abstract methods and provide for retrieval of this information. Further, each Font Handler subclass and instances thereof implement a specific interface that provides format specific capabilities. Font information is stored in instances of the Font Handler. A Font class is defined that provides application developers the ability to access the information from the Font Handler. When an application developer desires to use a particular font, the developer creates an instance of the Font class and establishes an association with a corresponding Font Handler instance.