Abstract: One embodiment of the present invention provides a system that camouflages business-activity information in telemetry signals from a computer system. During operation, the system monitors telemetry signals from the computer system to obtain a time series containing a telemetry metric which provides business-activity information. Next, the system computes a serial correlation between data values in the time series. The system then determines if the computed serial correlation between the data values in the time series is above a predetermined threshold level. If so, the system performs frequency domain analysis on the time series. The system then generates artificial activity on the computer system which causes the frequency spectra of the time series to reduce the serial correlation between the data values in the time series.

Abstract: A method and apparatus is provided to enable provision of requested data within two clock cycles when performing a swap operation between an accessible memory cell and a background memory in a computer. In a first clock cycle, memory addresses to be used in the swap operation are decoded. In a high phase of a second clock cycle, requested data is restored from the background memory to an accessible memory cell. Because the data previously stored in the accessible memory cell is duplicated in a shadow memory cell, the restoration of data to the accessible memory cell is performed without data loss. In a low phase of the second clock cycle, the requested data is available for reading. During a third cycle, data is saved from the shadow memory cell to the background memory, and the shadow memory cell is made consistent with the accessible memory cell.

Abstract: A system and method for ensuring non-interfering garbage collection in a real time multi-threaded environment. An incarnation counter is associated with a scoped memory area. The incarnation counter is atomically updated upon access by a no heap thread not interruptible by garbage collection operations. A write stub is identified and includes instructions to store data into storage locations of the scoped memory area. The instructions are dynamically modified to interrupt execution of a garbage collection thread. A garbage collection thread is executed over the scoped memory area. At least one of a read from the scoped memory area and a write to the scoped memory area are attempted. For the read attempt, an incarnation number is read from the incarnation counter of the scoped memory area and is locally stored. A value from a storage location in the scoped memory area is loaded and the incarnation number is reread. The reread incarnation number is compared with the locally stored incarnation number.

Abstract: The timing response of a circuit path is predicted by modeling the circuit path using two different timing models. The variation between the timing responses produced by each of the timing models is used to generate a correction factor, which is then applied to one of the timing models. Once the correction factor has been applied to a timing model, the model is used to produce a corrected timing prediction for the modeled circuit path.

Abstract: One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes the instruction and subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. Upon encountering a store during the execute-ahead mode, the system determines if the store buffer is full. If so, the system prefetches a cache line for the store, and defers execution of the store.

Abstract: One embodiment of the present invention provides a system that camouflages business-activity information in telemetry signals from a computer system. During operation, the system monitors telemetry signals from the computer system to obtain a time series containing a telemetry metric which provides business-activity information. Next, for each telemetry-metric value contained in the time series, the system compares the telemetry-metric value with a predetermined threshold level. If the telemetry-metric value is below the predetermined threshold level, the system then generates artificial activity associated with the telemetry metric in the computer system, so that the artificial activity causes the telemetry-metric value to exceed the predetermined threshold level.

Abstract: A system for communicating program data between devices includes a first device configured to disassemble a program file comprising program data into at least one logical data unit, partition each logical data unit into at least one protocol data unit and compute a first fingerprint over the payload portion of the protocol data units. The first device is also configured to send the protocol data units and at least one member of the group comprising the first fingerprint and a first authentication code based on the first fingerprint to a second device. The second device is configured to compute a second fingerprint over the payload portion of the protocol data units and to commit the program to a memory based on whether the at least one member matches the second fingerprint or a second authentication code based on the second fingerprint.

Abstract: Embodiments of the present invention provide a system that characterizes the reliability of a computer system. The system first collects samples of a performance parameter from the computer system. Next, the system computes the length of a line between the samples, wherein the line includes a component which is proportionate to a difference between values of the samples and a component which is proportionate to a time interval between the samples. The system then adds the computed length to a cumulative length variable which can be used to characterize the reliability of the computer system.

Abstract: A method for performing sensitivity analysis on a circuit design is provided. The method initiates with identifying a partition of the circuit design. The method includes determining whether the partition belongs to a sensitivity graph, where the sensitivity graph represents a relationship between variables and parameters of the partition. If the partition belongs to the sensitivity graph, then the method includes, applying linear matrix factors to provide a solution to a system of linear equations and multiplying the solution by a vector to derive sensitivities for the circuit design.

Abstract: An apparatus for measuring vibration of a fan includes a frame having an opening for enclosing a fan; a plurality of accelerometers disposed on the frame; and an elastic support for supporting the frame. An apparatus for measuring fan vibration includes a frame having an opening for enclosing a fan; a plurality of accelerometers disposed on the frame. The plurality of accelerometers output a signal to the signal-analyzing device and at least three of the plurality of accelerometers are disposed on a different surface of the frame from each other. The apparatus for measuring fan vibration includes a mounting block that allows the fan to be secured in the opening of the frame and an elastic support for supporting the frame. A method of measuring fan vibration includes disposing a plurality of accelerometers on a frame; mounting a fan within the frame; turning on the fan; and outputting a signal from each of the plurality of accelerometers to a signal-analyzing device.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention compute a multidimensional fast Fourier transform of an original matrix having rows and columns of data. The original matrix is divided into a number of blocks of data, each block including at least one datum, the number of rows of data in each block being less than a total number of rows of data in the original matrix. A one-dimensional partial fast Fourier transform of each block in a row of blocks is computed. A result of the computations is stored in a resultant matrix having rows and columns. The resultant matrix is transposed to a transposed matrix having rows and columns. While transposing the resultant matrix, one-dimensional partial fast Fourier transforms of each block of subsequent rows of blocks are simultaneously computed, one row of blocks at a time, until one-dimensional partial fast Fourier transforms are computed for each block.

Abstract: One embodiment of the present invention provides a system that facilitates identifying roots for a garbage-collection operation in a computer system that supports an object-addressed memory hierarchy. In order to identify roots, the system first looks up an object table entry that corresponds to an object in an object cache, wherein the object table entry contains an evicted bit, which is set when any part of the modified object is evicted from the object cache, and a corresponding physical address for the object in main memory. Next, the system determines if the evicted bit is set in the object table entry, and if so, examines the object corresponding to the object table entry to determine if the object contains references to the target area in the object heap that is being garbage collected. If so, the system uses the references as roots for a subsequent garbage-collection operation of the target area.

Abstract: An Infiniband switch can be provided. The switch can have an input port logic unit for determining an output virtual lane for a received packet and for storing a descriptor of the determined output virtual lane in a packet field not protected by a checksum field of the packet. The switch can also have a routing unit for transferring the received packet to an output port corresponding to the determined output virtual lane. Additionally, the switch can have an output port logic unit for simultaneously checking the integrity of the packet transferred through the routing unit and calculating a new value for the checksum with the descriptor moved to a correct packet field, which field is included in the calculation of the checksum.

Abstract: One embodiment of the present invention provides a system that detects changes in power-supply current within an integrated circuit (IC) chip. During operation, the system monitors an induced current through a detection loop. This detection loop is situated at least partially within the IC chip in close proximity to a power-supply current for the IC chip, so that a change in the power-supply current changes a magnetic field passing through the detection loop, thereby inducing a corresponding current through the detection loop. The system then generates a control signal based on the induced current, so that changes in the power-supply current cause the control signal to change. In addition, the system uses the control signal to control circuits within the IC chip.

Abstract: A method for faster handling of state change notifications in a storage network such as storage area network (SAN). The method includes receiving a state change notification at a host. The notification is processed to identify a target device affected by a state change. The method includes cleaning an input/output (I/O) resource of the host of I/O operations associated with the target device. A new session request is transmitted from the host to the target device, such as the next communication from the host after receipt of the notification. The cleaning of the host's I/O resources may include killing or abandoning pending I/O operations related to the target device and may also include halting or stopping additional or future I/O operations to the target device. The method includes operating the affected target device to acknowledge the new session request and initiate a new session that includes refreshing target I/O resources.

Abstract: A system that uses statistical techniques to selectively transmit data from a sensor. During operation, the system receives a sequence of quantized values from the sensor. The system then determines whether a distribution for the sequence of quantized values indicates that the sensor is observing a real event. If so, the system transmits sensor data for the real event to a receiver.

Abstract: An apparatus and method for non-destructive solder interconnect integrity monitoring that can detect existing fracture damage, identify new or incipient fractures, and be implemented across multiple component configurations. Said components can be implemented to detect, on a continuous basis, solder interconnect fractures as they occur during actual end-use, throughout the lifecycle of monitored components, rather than relying on a one-time electrical check prior to shipment.

Abstract: A system for applying distributed software simulation techniques to hardware emulation may include a first hardware emulator mounted on a first expansion board at a first host, and a second hardware emulator mounted on a second expansion board at a second host. The first hardware emulator may be configured to emulate a first portion of a system under test, and the second hardware emulator may be configured to emulate a second portion of the system under test, and the first and second hardware emulators may coordinate an emulation of the system under test using one or more messages, i.e., a coordination of an emulation of the system under test may be accomplished using communications between the first and second hardware emulators.

Abstract: A system and method for mapping software components (e.g., source files, binary files, modules) to test cases that test the components and providing rating information regarding each test case's effectiveness against its tested components. Each test case is applied to test a corresponding subset of the components, during which data are gathered (e.g., amount or elements of a component that were tested, which components were tested, time). Each test case is applied separately so that correlations between each test case and the corresponding subset of the software components can be recorded (and vice versa). A rating is generated to indicate how completely or effectively a test case covers a software component. A bipartite graph and/or other data structures may be constructed to map test cases to the software components they test, and vice versa.

Abstract: A method for locating a root block in file system metadata, includes traversing the file system metadata to locate a leaf block, wherein the leaf block comprises a plurality of root blocks and at least one of the plurality of root blocks is unallocated, allocating the at least of one the plurality of unallocated root blocks to obtain an allocated root block, wherein the leaf block is associated with a fill count and the fill count is less than a maximum fill count of the leaf block.