Abstract: A circuit for detecting manufacturing deficiencies in semi-conductor devices and selecting marketable chips comprises a speed circuit to determine the speed at which a particular chip operates. The speed circuit is a small, self-contained circuit that may be placed on any type of semi-conductor chip. It includes an oscillator, a counter, and a control logic circuit. The speed circuit is coupled to an external clock and a control processor. The external clock provides a benchmark against which the operation of the chip can be compared. The control processor uses the output of the speed circuit to compute the speed at which the semi-conductor device operates.

Abstract: A local area network is disclosed including apparatus and methods for transmitting data between a plurality of data processing resources (agents) coupled to a cable. An agent desiring to send data to a receiving agent transmits a request to send (RTS) data packet which includes a control character requesting to either high or low speed data communication. Utilizing the teachings of the present invention, absent other predefined conditions a transmitting agent capable of high speed communication requests a high speed data exchange with the receiving agent. The RTS data packet itself is transmitted at low speed. Upon receiving the RTS packet, the receiving agent must transmit a clear to send (CTS) packet to the transmitting agent within a predetermined time after the receipt of the RTS packet.

Abstract: An improved interface between a processor and an external cache system, having particular application for use in high speed computer systems. A cache memory for storing frequently accessed data is coupled to a cache address register (CAR). A processor generates addresses which correspond to locations of desired data in the cache, and provides these addresses to the CAR. Upon the receipt of a clock signal, the CAR couples the address to the cache memory. The processor includes a data register for receiving accessed cache data over a data bus. Data is latched into the register upon the receipt of a clock signal. Due to inherent delays associated with digital logic comprising the processor, clock signals provided by an external clock are received by the CAR prior to their receipt by the processor's data register. This delay (a fraction of a clock cycle) provides additional time to access the cache memory before the data is expected on the data bus.

Abstract: An improved display system which includes a central processing unit (CPU) coupled to a display utilizing vertical blanking intervals. A frame buffer memory is coupled to the CPU for storing data representative of color indices for each display pixel. The frame buffer is further coupled to look-up tables (LUTs) for storing color values which are provided through digital/analog converters (DACs) to the display. The CPU updates the contents of the frame buffer and/or LUTs during the vertical blanking interval of the display. A "first half" status flag is provided to the CPU at the beginning of each vertical blanking interval. This status flag remains true until one half of the period has elapsed. A "too late" status flag is also provided at the initiation of the interval which remains low until the end of the vertical blanking interval.

Abstract: A multi-input logic gate is disclosed having particular application for use as an AND or OR gate in a digital circuit. The OR gate of the present invention includes drive, sense and reference rails. A plurality of input lines are coupled to a gate of a plurality of N-channel transfers disposed between the drive and sense rails, one input line per transistor. The drive rail is coupled to ground through an N-channel transistor whose gate is controlled by the state of a detect line. The sense and reference rails are coupled to a voltage source (V.sub.dd) through P-channel transistors whose gate is also coupled to the detect line. The P-channel transistor coupled to the sense rail is sized to pass more current than the corresponding transfer on the reference rail. A sense amplifier is coupled to the sense and reference rails, and outputs a predetermined signal as a function of the voltage difference of the rails.

Abstract: An adaptive forward differencing apparatus wherein, when rendering curves, calculated x, y values are increased or decreased in order to create values which correspond to the next pixel of the display CRT, such that curves of substantially one pixel increments are continuously and uniformly generated. The apparatus of the present invention also provides circuitry for generating coordinates of display elements which approximate an ideal vector and to define curves, vectors or objects within maximum and minimum coordinates of the CRT display. The present invention also provides efficient circuitry for computing the value of 1/w of the homogenous coordinate w.

Abstract: A memory architecture having particular application for use in computer systems employing virtual memory techniques. A processor provides row and column addresses to access data stored in a dynamic random access memory (DRAM). The virtual address supplied by the processor includes high and low order bits. In the present embodiment, the high order bits represent a virtual row address and the low order bits represent a real column address. The virtual row address is applied to a memory management unit (MMU) for translation into a real row address. The real column address need not be translated. A comparator compares the current virtual row address to the previous row address stored in a latch. If the current row and previous row addresses match, a cycle control circuit couples the real column address to the DRAM, and applies a strobe signal such that the desired data is accessed in the memory without the need to reapply the row address.

Abstract: The present invention discloses apparatus and methods for direct memory access (DMA) having particular application for use in displaying digital images in an animated form on a CRT display. The present invention includes a DMA controller coupled over a bus to a frame buffer. The frame buffer includes one or more bit maps representative of the display. A block of memory within the frame buffer is mapped onto corresponding picture elements (pixels) on the display. The frame buffer continuously scans the bit map representing the CRT screen such that modifications to data bits within the frame buffer are correspondingly displayed on the screen. A plurality of windows may be displayed on the CRT having varying predefined widths which are appropriately represented within the frame buffer.

Abstract: An improved memory organization for use in a computer display system including a display having a plurality of display pixels for defining images that includes: a frame buffer memory having a plurality of memory cells organized into a matrix, said memory comprising first and second maps wherein the contents of the maps correspond to the pixels and define characteristics of the pixels, the maps being defined along X and Z axes of the matric; reading means coupled to the frame buffer memory for selectively reading, in one memory cycle operation, a plurality of bits from memory cells defining one of the maps; writing means coupled to said frame buffer memory for selectively storing, in one memory cycle operation, a plurality of bits into memory cells defining one of the maps; control logic means coupled to the reading means and the writing means for generating control signals for selectively reading a plurality of bits from one of the maps and writing a plurality of bits into one of the maps to define the images

Abstract: The present invention provides an improved arbitrator for use in allocating access to a common resource coupled to a plurality of data processing devices ("agents"). An arbitrator is coupled between the resource and each of the agents, for selectively enabling individual agents to access the resource in accordance with a predetermined priority hierarchy. The arbitrator, in the presently preferred embodiment, receives request signals transmitted by an agent desiring to access the resource and allocates ownership on a first come first serve basis or by a four level hierarchy in the case of simultaneous requests. The arbitrator includes a timing circuit which times predetermined periods between request signals transmitted by the agent which has acquired ownership. The arbitrator senses multiple requests for access by the agent within the predetermined time period, and, enters a lock condition if the agent issues a second request within the predefined period.

Abstract: A computer memory architecture is most advantageously used in conjunction with a digital computer, to provide an improved high speed graphics display capability. Data representative of digital images to be displayed is generated and/or manipulated by a display processor and stored within a selected portion of the display processor's main memory. Subsequent modifications to the stored image are effectuated by the display processor reading the data from its main memory, performing appropriate operations on the data, and writing the data back into the main memory. Updated images are transferred to an buffer memory which sequentially stores the images in the order in which they were updated by the display processor. Data representative of an updated image is then transferred to the display frame buffer of the particular display system for subsequent display. Data is transferred from the buffer memory to the frame buffer during periods when the frame buffer is not refreshing the display.

Abstract: The present invention provides apparatus and methods which are most advantageously used in conjunction with a computer display system incorporating the use of a Z-buffer to provide three dimensional hidden surface elimination. A buffer memory is provided which is sufficiently large such that each display element (pixel) on the display is represented by a 16-bit Z value. The Z value corresponds to the Z axis depth of the object at the particular point corresponding to the pixel. The buffer comprises a plurality of dynamic random access memories (D-RAMs) having two operation modes: Normal and Read-Modify-Write (RMW). A counter/pointer register is provided which successively addresses values in the buffer representing successive pixels along scan lines of the display. A graphics processor is provided with coordinates defining a three dimensional image to be displayed and, for each point of the object, computes a current Z.sub.c value beginning at an initial coordinate address in memory.

Abstract: An improved memory management system is described having particular application for use in computer systems employing virtual memory techniques. The system includes a CPU and other data processing devices, such as I/O devices, direct memory access (DMA) units, a system bus, etc., which are coupled to a "virtual" address bus for transferring virtual address information to a main memory unit (MMU). Access to the virtual bus is controlled by arbitration unit in order to insure that only a single device may communicate with the MMU at a time. In a preferred embodiment, address space within the MMU is allocated into a plurality of memory spaces, each space including translation data for use by a particular data processing device coupled to the virtual bus. A device gaining access to the virtual bus identifies the particular MMU memory space to be used for its address translation by providing unique context bits denoting the memory space to the MMU.

Abstract: A method and apparatus for accessing a particular location in a main memory of a computer in which virtual addresses from a CPU are separated into direct and indirect address segments. The direct address segment is applied directly to one of row and column control lines that identify such location in the memory and the indirect address segment is translated into a real address segment and applied to the other of the row and column control lines of the main memory that identify the particular memory location. The row and column control lines are strobed with sequential pulses such that the control line to which the direct address segment is applied is strobed prior to the control line to which the translated real address segment is applied.

Abstract: An apparatus for manipulating and displaying raster images stored in a memory system under computer control, wherein a function unit combines new display data presented to the apparatus with display data already stored in memory, to form a new display that is stored in memory system, all in a single read/modify/write cycle.