Abstract: In an arrangement for packaging planar arrays of circuit components including a plurality of essentially parallel layers in which the layers lie closely adjacent one another, one or more of the layers including a substrate of insulating material having circuit board apparatus imbedded therein, the improvement including apparatus positioned against at least one of the layers for removing heat from the arrangement.

Abstract: A standard polygon clipping algorithm is used to either trivially accept/reject the sides or clip the sides of a polygon. Then, for each side that cannot be trivially accepted/rejected nor clipped using the standard polygon clipping algorithm, at least one turning point is generated to replace the side by performing a Boolean operation using the region codings provided by the standard polygon clipping algorithm. As a result, the replacement turning points are generated using integer arithmetic.

Abstract: The method of rendering an X Windows server system running on a server and at least one host computer terminal secure including the steps of allowing users to view only resources of the X Windows server system the use of which has been specifically authorized to that user, and allowing users to manipulate only resources of the X Windows server system the use of which has been specifically authorized to that user.

Abstract: A binary integer multiplier including a plurality of adder stages, each of such adder stages including a plurality of cells equal to a number of bits in an operand, each of such adder stage including a pair of full adders capable of receiving six input bits and producing two result bits at the significance level of the cell and two carry bits at the next higher significance level, apparatus interconnecting the bits indicating partial products to the input terminals of a cell at each significance level, apparatus interconnecting the carry output terminals of a cell to input terminals of the cell at the next significance level, apparatus interconnecting one carry output terminal of a cell to any unused input terminal at a cell of a particular stage at which only three input signals are provided, and apparatus interconnecting the result terminals of each cell to the input terminals of the cell at the same significance level at the next adder level.

Abstract: Write handshake circuitry for an asynchronous bus interface system transferring data between sending and receiving computer systems including apparatus for providing a pre-acknowledge signal during the idle condition of the interface system to indicate to the sending computer system that the receiving system is ready to accept data, apparatus for synchronizing the pre-acknowledge signal to the clock of the sending computer system during the idle condition of the interface system, apparatus for providing a write signal from the sending computer system to indicate to the receiving computer system that the sending computer system is writing to the receiving computer system, and apparatus in the receiving system for receiving and synchronizing data upon the appearance of the write signal.

Abstract: A method and apparatus is described which fills in the pixels missed when drop-out occurs during the fill process of character contours. The character contour is decomposed into a series of rook moves. The pixel selected is the one more covered by the actual shape of the portion of the curve where the rook moves are coincident and dropout occurs. This is dependent upon the slope of each of the curves at the location of dropout. Preferably the length of the sequence of colinear consecutive rook moves is used to approximate the slopes of the curves. The target pixel of the longest sequence of colinear rook moves is more covered than its opposite pixel and therefore the target pixel is set. The target pixel for a rook move is the pixel in the winding direction (i.e., left or right direction) along the rook move. Thus the target pixel of the stronger rook moves will be set and added to the bit map image generated using a outline fill process.

Abstract: A three dimensional arrangement for packaging planar arrays of circuit components in a plurality of essentially planar layers in which the layers lie closely adjacent to one another is disclosed. Each layer is separated by a shell that interposes slots for allowing coolant to pass between the layers and electrical conductors through the shell, so that when the layers are placed together, the conductors form a bus through the structure.

Abstract: The present invention provides apparatus and methods to achieve a high speed bi-CMOS differential amplifier with controlled output voltage swing for use in amplifying low level complementary logic signals. The differential amplifier is comprised of a load current controller and a sense amplifier. The load current controller compares a desired reference voltage to the voltage drop across a simulated load. The load current controller then produces therefrom a bias voltage corresponding to the current which results in a voltage drop equal to the reference voltage. The bias voltage, when applied to the sense amplifier, limits the output of the sense amplifier to a controlled voltage swing of magnitude equal to the reference voltage.

Abstract: The present invention provides unique methods and apparatus for shading curves, polygons and patches, implementing Phong, Gouraud and other shading techniques in the rendering of images on a cathode ray tube or other display device. The present invention also includes a unique method and apparatus for shading patches by rendering a series of adjacent curves such that no pixel gaps exist between each rendered curve.

Abstract: An asynchronous micro-machine/interface responsive to a central processing unit (CPU) in which the CPU and the micro-machine/interface are run on clocks which are asynchronous from one another is provided. The inventive asynchronous micro-machine/interface has data path elements for receiving an incoming instruction and for performing actions requested by the incoming instruction, as well as a means for synchronizing the incoming instruction to the clock of the micro-machine/interface and for performing actions within the data path elements prior to the execution of the incoming instruction and during transfer of control, by the micro-machine/interface, to the routine that is associated with the incoming instruction.

Abstract: An arrangement for packaging thin planar arrays of circuit components including a plurality of essentially thin parallel layers in which the layers lie closely adjacent one another, one or more of the layers including a substrate of insulating material having circuit board means imbedded therein, the improvement including heat-conducting means positioned against at least one of the layers for removing heat from the arrangement, the heat-conducting means having an interior channel for transferring a fluid to accomplish the heat removal, and means providing electrical conduits through the heat-conducting means.

Abstract: A computer construction particularly suited for desktop computers whereby the computer may be opened to provide access to substantially all of the functional components thereof for trouble shooting, maintenance and repair purposes without disconnection of any of the interconnects within the computer and without any interference with the connectability thereof with the outside world, whereby the computer and the input/output functions thereof may be fully functional and exercisable when the computer is so opneed. The computer housing is split into upper and lower housing assemblies with the mother board fastened into the lower portion of the lower housing assembly and the power supply, cooling fan and disk drives fastened into the upper housing assembly.

Abstract: An apparatus for rapidly switching between output display frames using a shared frame identification memory is disclosed which has particular application to high resolution graphics for animation. Through a plurality of comparison circuitry, the apparatus enables a frame to be displayed during the clock cycles when the frame identification memory is read and during the clock cycles when the frame identification memory is provided with input, thereby, allowing a frame identification memory to be shared by two output display memories. As a result the rapid switching between output display frames sufficient for animation may be achieved with less hardware.

Abstract: A method and apparatus for precisely varying the display rate of computer generated graphic images. These images are generated by a computer system. The images are made up of a plurality of individual cells. Each cell is a picture of the object at a different point in time. With the present method, the user inputs the desired display rate into the computer system. The computer then converts this display rate into a vector located in the first quadrant of an x,y coordinate system. In this system, the x-axis represents increasing time and the y-axis represents cell number. The vector is displaced away from the x-axis through an angle. Theta is a predetermined function of the previously entered display rate. The first cell in the image is displayed, and the computer waits for a fixed interval of time. After this wait period, the computer uses a simple algorithm to check the height of the vector above the x-axis. If the vector is above a specified height, then the next cell is displayed.

Abstract: A computer output system having a first full screen bitmapped memory, a second full screen bitmapped memory, logic circuitry for providing input signals for writing information to be displayed by an output device to each position of the first memory, logic circuitry for storing in the second memory the positions of each position of the first memory to be written to the output device, and logic circuitry for comparing the signal stored at each position of the first memory and the signal stored at the same position of the second memory to determine whether information at the position is to be written to the output device.

Abstract: A first number conversion circuit for converting input numbers in the form of an integer, a floating-point number and a FRACT number into Modulo 256 format for use in connection with a graphic accelerator capable of rapidly manipulating numbers in Modulo 256 format. Also, a second number conversion circuit is disclosed for converting numbers in Modulo 256 format into output numbers in the form of an integer, a floating-point number and a FRACT number after manipulation by the graphic accelerator.

Abstract: The present invention is a deckside computer workstation housing which includes a frame assembly having at least one vertically oriented slot formed therein for insertion of a plug-in circuit board in a vertically oriented manner.

Abstract: A circuit for decomposing a graphic figure to be displayed by a computer output display into pairs of line segments which line segments outline the figure comprising apparatus for providing signals indicative of the vertices of a figure to be displayed, apparatus for providing comparisons of the relative positions of such vertices as they are to be displayed, apparatus for selecting a starting vertex for determining the line segments which include common scan lines, apparatus for selecting a first line segment connected to the starting vertex, apparatus for selecting a second line segment connecting to the starting vertex; and apparatus for providing output signals indicative of line segments selected.