Abstract: A rounding circuit for a binary tree floating point multiplier including apparatus for providing the upper bits of a mantissa presuming that no carry-in has occurred without waiting for the generation of a carry-in from lower order bits, apparatus for providing the upper bits of a mantissa presuming that a carry-in has occurred without waiting for the generation of a carry-in from lower order bits; apparatus for providing a first set of lower order bits for the mantissa based on an actual carry-in from a lower order bit adder and a rounding condition, the first set of lower order bits for the mantissa being chose for no mantissa overflow; apparatus for providing a second set of lower order bits for the mantissa based on an actual carry-in from a lower order bit adder and a rounding condition, the second set of lower order bits for the mantissa being chosen for mantissa overflow; and apparatus for selecting upper order bits and lower order bits for the mantissa based on whether a carry-in propagates past the l

Abstract: An arrangement for writing to and reading from the random access ports of a multibank frame buffer so that individual pixels to be presented in a vertical line on an output display are arranged sequentially from top to bottom in different banks of the frame buffer.

Abstract: The method allows for the loading of operating systems between computers over a network, thereby drastically decreasing the amount of time required to download an operating system or update an operating system. A root directory is created and a subset of the operating system is loaded into the memory of the computer which is to receive the operating system, thereby eliminating the need to access or use the disk during the operating system download process. The subset of the operating system contains the basic commands for file creation and manipulation, directory creation and network communication. The computer system is then started using the subset of the operating system located in memory and connected to the network. Once the computer is connected to the network, the files comprising the operating system to be downloaded are copied and transferred from a remote computer over the network and stored on the disk drive of the receiving computer.

Abstract: Apparatus and method for using an index register which cycles modulo 4 for loading registers which contain coordinates of four vertices of quadrilateral objects, including degenerate quadrilateral objects, namely a point, a line and a triangle, which are to be displayed by a graphics display subsystem. In this manner, a software command need only define the minimum number of X,Y coordinate pairs to define the object, i.e., one coordinate pair for a point, two coordinate pairs for a line, three coordinate pairs for a triangle and two coordinate pairs for a rectangle (by defining opposite corners). Additionally, by using an index register according to the present invention, objects can be efficiently replicated.

Abstract: The present invention provides to the software application the verification and license check out functions which are normally performed by a license server of a network software license system. The encrypted license information is contained in a license token, and is sorted in the database controlled by the license server. In contrast to the prior art where the license server either grants or denies the request after verifying the user's credentials, the license server in the preferred embodiment of the present invention finds the correct license token for the software application and transmits the license token to the licensing library. In application specific license access module attached to the application decodes the licensing token. Routines in the licensing library coupled to the software application verify the license information before checking out the license and updating the license token.

Abstract: Circuitry for performing high speed operations on certain Boolean raster operations in a workstation whose functions include the display of graphics images using multiple planes and having foreground and background colors. The circuitry includes a logic circuit for determining whether a particular Boolean raster operation is one for which the high speed operation is available. A Boolean raster operation is determined to be available for high speed operation if the outcome of the operation can be determined by reading only one operand, namely the source data. If the other operand, namely the destination data, is needed to determine the outcome if the operation, then the operation is performed normally. Otherwise, the operation may be performed by reading the source data only.

Abstract: A caching memory system including a translation look-aside buffer having a preselected number of lines of memory, each of said lines including storage for a virtual address and a physical address, apparatus for selectively varying the size of pages the virtual and physical addresses of which may be stored in the translation look-aside buffer, and apparatus for interrogating the virtual addresses to determine whether a requested address is stored in the translation look-aside buffer.

Abstract: A cylindrical body is provided over an ultrasonic flux nozzle. The cylindrical body contains a cavity inside generating a vacuum when the flux nozzle in in operation. Additionally, the portion of the top surface of the cylindrical body that is adjacent to the output of the flux nozzle has passageways for drawing off excess flux into the cavity. As a result, flux that exits the nozzle in an atomized vapor form is limited to a fine stream, thereby allowing the amount of flux to be deposited on a desired area to be precisely controlled.

Abstract: A method of initiating a write operation for a particular command from a first computer module through a system interface to a second computer module having data registers, and a status register which includes the steps of writing data to the data registers in the second computer module, and determining the status of the status register in the second computer module to cause the initiation of the particular command by which the reading the status of the data registers and issuing the particular command as separate steps are eliminated.

Abstract: A circuit for determining the X values of each end of a series of horizontal scan lines connecting a pair of line segments each of which is defined by a pair of vertices, the horizontal scan lines defining an area to be rendered on a computer output device, comprising first and second circuit portions, each of said circuit portions including apparatus to determine the slope of a line segment, apparatus depending on the slope for determining the beginning and ending X values for each line segment for each scan line in the area to be rendered, apparatus for causing the two circuit portions to begin operation at the same scan line, and apparatus for changing the Y value for each circuit portion to the Y value of the next adjacent scan line at the same time.

Abstract: Each database component file contains information regarding the text contained in the source file which enables the user to quickly determine the frequency of occurrence of the specified text and the location of the specified text in the source file. For each textual word (referred to herein as a "symbol") an entry in the database file is provided containing symbol information. The symbol information comprises the symbol name, symbol type and line number in the source file where the symbol is located. Line indentification information is also provided which contains the line numbers in the source file and corresponding line lengths and hash values which are computed from the contents of the lines of the text in the source file. Before a line of text identified in a query is displayed to the user indicating a result of the query, the line identification information provides the means to verify that the line of text identified in the symbol information is the same line of text contained in the source file.

Abstract: The system of the present invention provides for the context switching of devices connected through the system's memory management unit and is particularly useful in a multi-tasking computer system in which multiple processes access the same device. In the method and apparatus of the present invention, devices that are connected to the system through the MMU are controlled using the page fault mechanism of the MMU and the page fault handler in each segment. Addresses are allocated in the process address space for each process to provide for the addressing of the devices and device queues connected through the MMU, such that one device or one device queue is mapped into one segment of each process address space that will access the device. The "valid bits" associated with each page in a segment are turned on/off by the process or operating system in order to control the device.

Abstract: An apparatus for testing computer chips and their assopciated system in their normal operating environment is disclosed. The elements of the apparatus including the receiving elements, the mounting elements and the test equipment coupling elements are disposed on a circuit board in a manner allowing the apparatus mounted with the removed computer chips, to be mounted to a host board in a manner, thereby enabling the comptuer chips to be tested without having to tilt or otherwise move the host board. As a result, testing of the computer chips is accomplished in a more efficient and cost effective manner.

Abstract: An adaptive forward differencing apparatus wherein, when rendering curves, calculated x, y values are increased or decreased in order to create values which correspond to the next pixel of the display CRT, such that curves of substantially one pixel increments are continuously and uniformly generated. The apparatus also provides circuitry for generating coordinates of display elements which approximate an ideal vector and to define curves, vectors or objects within maximum and minimum coordinates of the CRT display. The present invention also provides efficient circuitry for computing the value of 1/w of the homogenous coordinate w.

Abstract: A scan conversion process is performed on a polygon using a single pass technique. The pixels which comprise the edges and vertices of the polygon are first determined from the vertices which define the polygon. The alpha channel comprises either a sub-pixel mask associated with each pixel which indicates the amount and sub-pixel regions of coverage or a single value indicative of the percentage of coverage of a pixel. Furthermore, a z value indicative of the depth of each pixel is maintained. The pixels between the edge pixels of the polygon are then turned on, thereby filling the polygon. The pixels which comprise the polygon are then composited with the background pixels on a per pixel basis. The depth value of each pixel of the polygon (the z value) is used to determine the compositing equations to be used to composite each pixel of the polygon to the background.

Abstract: An improved high speed data transfer bus with virtual memory capability is disclosed. The bus has particular applications in computer systems which employ peripheral devices. The bus allows high speed data transfer through the use of a virtual memory scheme. Moreover, the present invention minimizes the number of lines required to implement the bus. The present invention also minimizes the amount of time a particular device is required to wait before it can access the bus and complete a data transfer. Moreover, the present invention employs control signals that are driven both active and inactive, facilitating interfacing the bus to low-power CMOS technology.

Abstract: A Tape Automated Bonding (TAB) process prepared multi-chip module (MCM) has semiconductor dice embedded into the substrate of the MCM through its top face. A heatsink, which in a preferred embodiment is a copper slug, is emplaced into the underside of the substrate so that the bottom surfaces of the dice engage the heatsink. A compliant, heat-conducting thermoplastic material is used to secure the dice to the heatsink and to maintain a good heat flow path. According to the present invention, the TAB formed component has beam leads that do not require bending to facilitate assembly. Rather, the beam leads are trimmed to length, leaving straight outer beam leads that, after the die is installed in the substrate, extend parallel to and overlie the top face of the substrate. The beam leads are thus positioned for convenient bonding to signal paths laid out on the top face of the substrate.

Abstract: An interface which includes a MIDI send terminal having first and second pins for providing an output signal, an RS 232 terminal having first and second pins for receiving a signal from the MIDI send terminal, apparatus for coupling any MIDI output signal to the RS 232 terminal, the apparatus for coupling including apparatus for shifting a base level at which the signals are presented at the MIDI terminal to a base level at which the signals are received at the RS 232 terminal, apparatus for shifting the voltage swing of signals presented at the MIDI terminal to a voltage swing at which the signals are received at the RS 232 terminal, and apparatus for disabling the RS 232 terminal if a device to which the RS 232 terminal is connected would normally respond in an undesirable manner to unexpected data received on the RS 232 terminal.

Abstract: Improvements in workstations which utilizes virtual addressing in multi-user operating systems with write back caches, including operating systems which allow each user to have multiple active processes directed to the support of alias addresses, i.e., two or more virtual addresses which map to the same physical address in real memory Specifically, alias addresses are created so that their low order address bits are identical, modulo the size of the cache (as a minimum) for user programs which use alias addresses generated by the kernel, or wholely within the kernel. For alias addresses in the operating system, rather than user programs, which cannot be made to match in their low order address bits, their pages are assigned as "Don't Cache" pages in the memory management unit (MMU) employed by workstations which utilize virtual addressing.

Abstract: A database system for text files is employed which comprises a compiler which receives as input a description of the source file types or languages and search filter and outputs a tag set definition file and filter file to be used by the browsing mechanism. The tags set definition file is input to the database builder mechanism and is used by the database builder to select and translate the information from the input source file to a database component file. Thus, by providing a description of the source file type, any type of source file in any language can be input to the database system of the present invention to generate a database component file which may be subsequently reviewed and searched by the same browsing mechanism.