Abstract: In a computer graphics system in which information defining graphic images to be presented on an output display is available on a scan line basis for a pair of line segments subtending a portion of the an image to be presented. The information includes the slope of each line segment and the addresses of each line segment on each scan line. A circuit comprising two comparator subportions, each of the comparator subportions being adapted to process information regarding one edge of the portion of the image to be presented and including apparatus for receiving first signals representing values of both of the line segments to be procesed for one scan line. Comparing the signals to determine their relative X positions on the scan line, controlling the determination of the relative X positions and the slope of each line segment, and storing one of the signals compared.

Abstract: A pipelined register cache for increasing a computer processor's execution speed by reducing the time required to access register data. A register cache is implemented to keep often-used registers in high-speed storage immediately available to the processor's arithmetic and logic unit (ALU). The register cache is constructed using a number of individual register stages which are connected in series such that the register information contained in each register stage is passed from one register stage to the next in a First-In, First-Out (FIFO) queue arrangement. Each register stage stores a register address tag for identifying the particular primary register being represented in that register stage, and a data value representing the actual register contents. When a register that is not represented in the cache is needed for a calculation, the register information is first loaded from the primary register storage into the first register stage of the register cache.

Abstract: A method and apparatus is provided to directly render volumes from volume data whereby the resolution of the volume is not lost and the volume data is completely interactive with geometric data. The volume or portion of the volume to be rendered is aligned to a geometric primitive defined by a reference frame and a mapping function is generated relating the geometric primitive to the volume or volume portion. The mapping function relates each voxel in volume space to an element or point of the primitive. Thus, the volume is displayed as a function of the geometric primitive the volume or volume portion is mapping to. In the preferred embodiment the volume or portion of volume to be rendered is bound by one or more geometric primitives and a mapping is generated relating the geometric primitive, such as a 3-D polgon, to the volume.

Abstract: A balanced tree clock distribution network for an integrated circuit including a branching clock line of layered metal in which each branch of the clock line has equal resistance, apparatus for shielding the clock line on both sides in the same layer of material of the integrated circuit, and apparatus for providing jumpers for crossing the clock line at right angles in a different layer of material of the integrated circuit which jumpers apppear at the same preselected distances along each branch of the clock line.

Abstract: A computer system which includes a central processing unit including a first processing unit that performs basic processing functions and a co-processing unit that performs multiple specialized processing functions concurrently with the first processing unit, an arrangement for detecting the occurrence of a function causing an exception in a result produced by the coprocessing unit, an arrangement for specifying to the first processing unit any exception in a result produced by the coprocessing unit, an arrangement for using the first processing unit to implement any function which causes an exception in a result produced by the co-processing unit, an arrangement for storing the identification of the instruction being handled by the first processing unit when a function causing any exception in a result produced by the co-processing unit occurs, and an arrangement for determing the instruction which produced the exception.

Abstract: The present invention provides an apparatus and methods to reduce the stray magnetic fields created by the yoke assembly of a cathode ray tube (CRT) visual display device, and emitted from the CRT enclosure. A pair of closed wire loops are brought into contact with the yoke at the point where maximum magnetic radiation is emitted. The magnetic flux emitted from the yoke is coupled into the wire loop pair, inducing therein a current which flows so as to produce an opposing magnetic field to that produced by the CRT yoke. A capacitor in series in the second loop serves to increase the magnitude of the magnetic field produced by the second loop. Measured at a distance, the counteracting magnetic field reduces the total magnetic field emitted from the CRT enclosure.

Abstract: Apparatus and methods are disclosed which are most advantageously used with a digital computer for detecting the location of multiple cursors in a computer memory having parity bits. In one embodiment of the present invention, the normal parity checking scheme of the computer memory is modified, such that the parity bit is used to detect data locations containing cursor data. Writing new data to the frame buffer is implemented as a read-modified-write cycle. In another embodiment of the present invention, the parity checking of the computer memory is no longer used as such. Instead, the memory controller has a mode that forces the parity bit to one of two states, independent of the contents of the data location. Rather than writing to the frame buffer as a read-modify-write cycle, the memory controller detects the location of the cursor by reading the state of the parity bit while writing the contents of the data location associated with the parity bit.

Abstract: A tristate driver circuit including a first output transistor for furnishing a first output voltage at an output terminal in the on condition, the first transistor being susceptible to disablement or degraded operation from back biasing in the presence of voltages above a particular level at the output terminal in the off condition, a second output transistor for furnishing a second output voltage at the output terminal in the on condition, apparatus for biasing the first and second transistors to allow operation thereof in the presence of enable signals and to disable operation in the absence of enable signals, and apparatus for eliminating back biasing of the first transistor in the absence of enable signals.

Abstract: Visible Moire interference is eliminated by alternately shifting the phase of the horizontal sync signal or video signals such that the phase of each video line, and hence the phase of the resulting Moire interference associated with that video line, is also alternately shifted. The phase of the Moire interferences are shifted such that persistence of vision in the human eye averages oppositely phased phosphor intensity variations occurring on alternating scan lines and/or vertical fields. When viewed by a user of the CRT, optical cancellation of the Moire interference patterns results.

Abstract: A computer system which has a display memory for storing information to be presented on an output display, and a full screen bitmapped window identification memory for storing information regarding window position on an output display, and uses circuitry for comparing incoming information with information stored in the window identification memory to determine whether the incoming information should appear in a particular window of the output display, and also includes a second full screen bitmapped memory normally utilized for storing information indicative of other than window position on an output display and utilizes circuitry for selectively storing information in the second memory regarding window position on the output display when additional windows are required.

Abstract: An improved high speed data transfer bus with virtual memory capability is disclosed. The bus has particular applications in computer systems which employ peripheral devices. The bus allows high speed data transfer through the use of a virtual memory scheme. Moreover, the present invention minimizes the number of lines required to implement the bus. The present invention also minimizes the amount of time a particular device is required to wait before it can access the bus and complete a data transfer. Moreover, the present invention employs control signals that are driven both active and inactive, facilitating interfacing the bus to low-power CMOS technology.

Abstract: A fan assembly with a single fan housing that has at least one fan passage adapted to allow air to flow through the housing. A separate fan subassembly is snapped into a motor housing formed within the passages of the fan housing. The subassembly includes an electric motor that rotates an impeller. The rotation of the impeller creates an airflow through the air passage. Attached to the surface of the housing is a conductor that extends from the motor, to an electrical connector that supplies power to the motor from an external power source. The air passage has rounded entrances and is formed such that the passage is shaped like a venturi tube. The rounded edges reduce the head loss through the passage by an order of magnitude, decreasing the pressure drop across the housing and improving the overall efficiency of the fan.

Abstract: A file system locking mechanism is provided which prevents the errors which arise when race conditions occur in a multitasking system. Atomic operators are utilized to perform certain operations for the creation and renaming of files and directories in the file system wherein if a race condition occurs, the atomic operations fail and the file creation process is halted to a predetermined state whereby the errors which occur during race conditions are prevented.

Abstract: A computer system comprising a display memory, a window indentification memory, logic circuitry for ascertaining that information to be stored at each position of the display memory is in the correct window by comparing the window number in the window identification memory with the window number of information to be sent to the display memory, and a window identification look-up table activated by window identification signals for providing an output to select the number of bits of color information to be output from the display memory to provide color information for an output device.

Abstract: In the system of the present invention, the performance of distributed window systems which employ shared libraries is provided. A shared library is a library which is referenced and accessed by multiple processes. Synchronization events are preset in a journal file which, during playback of the same, trigger a mechanism which reads the page table of the current applications. Once the playback is complete, the page table measurements taken during playback are reviewed and information is extracted which is used to determine the working set for shared libraries. Using the working set, the number of pages referenced and the rate of reference can be used to improve performance and predict behavior of other systems.

Abstract: An integer processing unit for a reduced instruction set computer having a plurality of registers arranged in groups referred to as register windows, each window register group including a number of input registers, a similar number of output registers, and a number of local registers, the register window groups being physically arranged so the input registers of each group are the same physical register as the output registers of the next adjacent register window group thereby forming one large interconnected ring of register window groups, an arrangement for designating the register window group presently active, and an arrangement for designating register window groups which are not available for use.

Abstract: Handshake circuitry for an asynchronous bus interface system transferring data between first and second computer systems including apparatus for providing signals to indicate to the second computer system that the first system desires to read data at a specified adress of the second system, apparatus for comparing the specified address with addresses of the second system to provide outputs indicating the time required to retrieve data from the specified address, and apparatus operative in response to the output indicating the time required to retrieve data from the second computer to indicate to the first computer system the time at which the information will be available for transfer to the first computer system.

Abstract: An apparatus and method for processing graphical information in a manner such that 1) accesses to a frame buffer in which the graphical information is to be stored result in a minimum of page crossings in the frame buffer; and 2) time spent processing graphical information outside a predetermined clip window is minimized. These two goals are sometimes conflicting and the present invention determines how the graphical information should be processed so that frame buffer accesses are always performed with the least overhead. For a given object which is to be displayed within a defined window, by determining the portions of the object which are inside the window and the portions which are outside the window, it frequently is possible to determine whether the object should be drawn from top to bottom, bottom to top, left to right or right to left so as to minimize page crossings and minimize the time spent processing portions of the object outside a predetermined clip window.