Patents Assigned to Sun Microsystems
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Publication number: 20080120619Abstract: A system, apparatus, and method are directed to enabling a user to analyze real-time scheduling decisions of resources in a computing environment. A scheduler component maps jobs to resources, and schedule jobs for execution. In one embodiment, the scheduler component continually iterates, based on job characteristics, available resources, required resources, policies, or other constraints. While the scheduler component performs its tasks, a scheduling trace interface (STI) component may perform a trace of decisions made by the scheduler component, as well as collect static and/or dynamic state information used by the scheduler component. In one embodiment, the STI component may generate a snapshot of the scheduling decisions, and state information. A user interface may be employed to query the scheduling snapshots to monitor and analyze the scheduling decisions, and state information. In one embodiment, the user may then modify a job, the job's requirements, or the like, based on the analysis.Type: ApplicationFiled: November 16, 2006Publication date: May 22, 2008Applicant: Sun Microsystems, Inc.Inventor: Sharma R. Podila
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Publication number: 20080120474Abstract: A method for processing using a shared file that includes creating a plurality of mmaps between a shared file and a plurality of address spaces, wherein each of the plurality of mmaps maps at least a portion of the shared file to one of the plurality of address spaces, and wherein each of the plurality of address spaces is associated with one of a plurality of processors, transferring, in parallel, data between the shared file and the address spaces using the plurality of mmaps associated with the plurality of address spaces, processing the data in parallel by the plurality of processors to obtain a result, wherein the plurality of processors access data from the plurality of address spaces, and storing the result in the shared memory.Type: ApplicationFiled: November 17, 2006Publication date: May 22, 2008Applicant: Sun Microsystems, Inc.Inventors: Andrew B. Hastings, Alok N. Choudhary, Harriet G. Coverston
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Publication number: 20080120476Abstract: A method for processing using a shared file that includes allocating a first working buffer between the shared file and a plurality of address spaces, wherein each of the plurality of address spaces is associated with one of a plurality of processors, copying first data from the shared file to the first working buffer by a first aggregator copying the first data from the first working buffer to the plurality of address spaces by the first aggregator, processing the first data, in parallel, by the plurality of processors to obtain a result, wherein the plurality of processors access data from the plurality of address spaces, and storing the result in the shared memory.Type: ApplicationFiled: November 17, 2006Publication date: May 22, 2008Applicant: Sun Microsystems, Inc.Inventors: Andrew B. Hastings, Anton B. Rang, Alok N. Choudhary
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Publication number: 20080116275Abstract: An embedded device includes a web interface configured to receive a request for an electronic product information (EPID) report, and send the request to a request handling service. The embedded device further includes the request handling service, configured to deploy one or more event handling components based on the request. The embedded device further includes the one or more event handling components configured to generate an EPID event cycle based on an EPID read cycle, according to an event cycle boundary condition, generate the EPID report based on the EPID event cycle, and transmit the EPID report to a client. The embedded device further includes a reader adapter configured to obtain the EPID read cycle, and transmit the EPID read cycle to the one or more event handling components.Type: ApplicationFiled: October 25, 2006Publication date: May 22, 2008Applicant: Sun Microsystems, Inc.Inventors: James B. Clarke, Cynthia Joann Osmon
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Patent number: 7376855Abstract: Input/output data transmission between a transmitting integrated circuit and a receiving integrated circuit requires a clock domain synchronizer to synchronize incoming data aligned to a clock signal of the transmitting integrated circuit to a clock signal of the receiving integrated circuit. During a start-up routine, the clock domain synchronizer propagates a pre-determined pattern of data bits through a first circuit path designed to reduce or eliminate metastability. During a normal operations mode, the clock domain synchronizer synchronizes the data signal to the clock signal of the receiving integrated circuit through a second circuit path.Type: GrantFiled: May 20, 2004Date of Patent: May 20, 2008Assignee: Sun Microsystems, Inc.Inventors: Claude R. Gauthier, Aninda K. Roy
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Patent number: 7376679Abstract: One embodiment of the present invention provides a system that facilitates delayed block allocation in a distributed file system. During operation, the system receives a write command at a client, wherein the write command includes a buffer containing data to be written and a file identifier. In response to receiving the write command, the system reserves a set of disk blocks for the file from a virtual pool of disk blocks allocated to the client. The system also transfers the data to be written to the kernel of the client where the data waits to be transferred to the disk.Type: GrantFiled: November 1, 2002Date of Patent: May 20, 2008Assignee: Sun Microsystems, Inc.Inventor: Shankar Pasupathy
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Patent number: 7376758Abstract: A method for executing a selected input/output (I/O) command from a plurality of I/O commands based on a dependency graph of I/O commands includes building the dependency graph of I/O commands, wherein the dependency graph is built by requiring all children of the selected I/O command to be ready before the selected I/O command is ready, and executing the I/O command based on the dependency graph, wherein execution of the selected I/O command is completed when all of the children of the selected I/O command finish execution.Type: GrantFiled: April 20, 2006Date of Patent: May 20, 2008Assignee: Sun Microsystems, Inc.Inventors: Jeffrey S. Bonwick, William H. Moore
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Patent number: 7376916Abstract: One embodiment of the present invention provides a system which performs a constrained optimization of circuit parameters. During operation, the system selects two circuit parameters associated with a circuit path, wherein the optimization is to be performed on the first circuit parameter while a limitation on second circuit parameter functions as a constraint on the optimization of the first circuit parameter. Next, the system generates objective functions which model the first circuit parameter and the second circuit parameter in terms of logical effort. The system then uses the objective functions to generate a constraint expression, wherein the constraint expression mathematically relates the optimization of the first circuit parameter to the constraint on the second circuit parameter. Next, the system computes a trade-off curve using the constraint expression. The system then computes transistor sizes for the circuit path based on a selected point from the trade-off curve.Type: GrantFiled: April 20, 2005Date of Patent: May 20, 2008Assignee: Sun Microsystems, Inc.Inventors: Jo C. Ebergen, George J. Chen
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Patent number: 7376940Abstract: Mechanisms can be used to facilitate suspension of a mutator thread (or mutator threads) while imposing negligible overhead on the mutator computation during periods when thread suspension is not requested. Mechanisms are provided to spill values from a fixed set of resources to a secondary store and to fill values from the secondary store into the fixed set in correspondence with function call triggered overflows and function return triggered underflows. In some configurations, modified spill and/or fill mechanism(s) are used to suspend threads at safe points coinciding with call and/or return sites. Because the modified spill and/or fill mechanism(s) impose negligible overhead when not employed and can be engaged in response to an event (e.g., a start garbage collection event), safe points can be defined at call and/or return points throughout mutator code to reduce the latency between the event and suspension of threads.Type: GrantFiled: June 4, 2004Date of Patent: May 20, 2008Assignee: Sun Microsystems, Inc.Inventors: William Bush, Mario Wolczko
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Patent number: 7376793Abstract: A system and method for performing speculative writestream transactions in a computing system. A computing system including a plurality of subsystems has a requesting subsystem configured to initiate a writestream ordered (WSO) transaction to perform a write operation to an entire coherency unit by conveying a WSO request to a home subsystem of the coherency unit. The requester is configured to perform the write operation without first receiving a copy of the coherency unit and complete WSO transactions initiated in the order in which they are initiated. The home subsystem is configured to process multiple WSO transactions directed to a given coherency unit in the order in which they are received. When the requester initiates a WSO transaction to a given coherency unit, the coherency unit is locked. Responsive to receiving the WSO request, the home subsystem conveys a pull request for the write data to the requester.Type: GrantFiled: July 21, 2005Date of Patent: May 20, 2008Assignee: Sun Microsystems, Inc.Inventors: Robert E. Cypher, Anders Landin
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Patent number: 7376657Abstract: A method for inserting a first prefix, including segmenting the first prefix into a first plurality of segments, indexing into a first trie node block using a first segment of the first plurality of segments to obtain a first trie node, obtaining a second segment of the first plurality of segments, determining whether the second segment of the first plurality of segments includes contiguous zeros, if the second segment includes contiguous zeros determining a number of contiguous zeros, determining a first skip level using the number of contiguous zeros, and inserting the first skip level into the first trie node.Type: GrantFiled: April 30, 2004Date of Patent: May 20, 2008Assignee: Sun Microsystems, Inc.Inventor: Ashish K. Mehta
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Patent number: 7374099Abstract: An application identifier (AID) for an application installed on a smart card comprises a registered application provider identifier (RID). The AID may be processed by determining the RID for an application from the AID of the application, generating an identifier for a network resource from the RID, transmitting a request to the network resource using the identifier, and receiving a response to the request. The response comprises material for use in handling the application on the smart card.Type: GrantFiled: February 24, 2004Date of Patent: May 20, 2008Assignee: Sun Microsystems, Inc.Inventor: Eduard K. de Jong
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Patent number: 7376683Abstract: The analysis of the lifetime of objects in a garbage-collected system may be accomplished quickly and effectively using reference counts and cyclic garbage analysis. A reference count is maintained for each of the objects to indicate the number of incoming pointers. Each time the graph structure is altered, the reference counts are updated. Timestamps are recorded each time the reference count for objects change. If a reference count goes to zero, the corresponding object may be indicated as dead. A garbage collection need only be run once (perhaps at the end), and after it is run the system may indicate which objects are cyclic garbage. The timestamps for objects which are cyclic garbage are then reviewed in reverse chronological order. For each timestamp found, the corresponding object and any object reachable from the corresponding object are indicated as dead. These objects are then removed from the set of cyclic garbage.Type: GrantFiled: March 8, 2004Date of Patent: May 20, 2008Assignee: Sun Microsystems, Inc.Inventors: Mario Wolczko, Antonio Cunei
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Patent number: 7373504Abstract: A method for performing a cryptographic function including calling into an encryption framework to perform the cryptographic function, wherein calling into the encryption framework comprises sending a request to perform the cryptographic function from a kernel consumer, and processing the request and returning the result to the kernel consumer, wherein processing the request comprises determining whether the request is synchronous or asynchronous, and determining which cryptographic provider to use to perform the cryptographic function.Type: GrantFiled: March 18, 2004Date of Patent: May 13, 2008Assignee: Sun Microsystems, Inc.Inventors: Kais Belgaied, Mark C. Powers, Bhargava K. Yenduri, Nicolas G. Droux, Paul J. Sangster, Darren J. Moffat, Gary W. Winiger
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Patent number: 7373368Abstract: A multiply execution unit that can generate the integer product of a multiplicand and a multiplier and is also operable to generate the XOR product of the multiplicand and the multiplier. The multiply execution unit includes a summing circuit for summing a plurality of partial products. The summing circuit includes a plurality of rows. The summing circuit can generate an integer sum of the plurality of partial products and can generate an XOR sum of the plurality of partial products. The summing circuit includes a plurality of compressors in the first row of the summing circuit. The plurality of compressors each has more than three inputs that receive data, a carry output, and a sum output.Type: GrantFiled: July 15, 2004Date of Patent: May 13, 2008Assignee: Sun Microsystems, Inc.Inventors: Leonard D. Rarick, Shu-Chin Tai
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Patent number: 7373461Abstract: In one embodiment, a node for a multi-node computer system comprises a coherence directory configured to store coherence states for coherence units in a local memory of the node and a coherence controller configured to receive a coherence request for a requested coherence unit. The requested coherence unit is included in a memory region that includes at least two coherence units, and the coherence controller is configured to read coherence states corresponding to two or more coherence units from the coherence directory responsive to the coherence request. The two or more coherence units are included in a previously-accessed memory region, and the coherence controller is configured to provide the requested coherence unit with a predicted coherence state responsive to the coherence states in the previously accessed memory region.Type: GrantFiled: April 28, 2006Date of Patent: May 13, 2008Assignee: Sun Microsystems, Inc.Inventors: HÃ¥kan E. Zeffer, Erik E. Hagersten
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Patent number: 7372657Abstract: In one embodiment, a method and apparatus for minimizing unload times in a tape drive system is disclosed. The method includes: writing to a tape in serpentine format; reaching a comparison point on the tape, wherein at the comparison point an actual capacity is compared to an expected capacity; utilizing the comparison at the comparison point to estimate a distance from the comparison point until a guaranteed capacity for the tape is reached; and determining a turn-around point on the tape based on the estimated distance, wherein at the turn-around point a tape drive writing to the tape to stop writing in a first direction and then continue writing in a second direction opposite from the first direction and towards a physical beginning of the tape. Other embodiments are also disclosed.Type: GrantFiled: May 24, 2006Date of Patent: May 13, 2008Assignee: Sun Microsystems, Inc.Inventors: Richard Allen Gill, Bradley E. Whitney
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Patent number: 7373500Abstract: In one general aspect, a network communication unit is disclosed that includes a cryptographic record parsing offload engine that has an input and an output. The unit also includes a processor that includes cryptographic handshake logic and has an input operatively connected to the output of the cryptographic record parsing offload engine.Type: GrantFiled: April 15, 2003Date of Patent: May 13, 2008Assignee: Sun MicroSystems, Inc.Inventors: Brian Ramelson, Stephen Metzger, Paul Phillips, Rajesh Vaidheswarra
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Patent number: 7373489Abstract: An apparatus and method for floating point exception prediction and recovery. In one embodiment, a processor may include instruction fetch logic configured to issue a first instruction from one of a plurality of threads and to successively issue a second instruction from another one of the plurality of threads. The processor may also include floating-point arithmetic logic configured to execute a floating-point instruction issued by the instruction fetch logic from a given one of the plurality of threads, and further configured to determine whether the floating-point instruction generates an exception, and may further include exception prediction logic configured to predict whether the floating-point instruction will generate the exception, where the prediction occurs before the floating-point arithmetic logic determines whether the floating-point instruction generates the exception.Type: GrantFiled: June 30, 2004Date of Patent: May 13, 2008Assignee: Sun Microsystems, Inc.Inventors: Jeffrey S. Brooks, Paul J. Jordan, Rabin A. Sugumar
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Patent number: 7373326Abstract: A system for developing and using a request for transaction framework including a framework engine configured to enable a market maker to develop a request for transaction for a particular market, and a request for transaction engine configured to enable an organization within the relevant market to prepare a request for transaction relating to a resource requirement and select a response relating to the resource requirement. In a preferred embodiment, the market maker creates a request for transaction framework by manipulating attribute parameters and identifying an analysis framework. A request for transaction framework may be a request for proposal framework, a request for quote framework, or other type of framework in which there is a request followed by a plurality of responses and a selection of one of the responses.Type: GrantFiled: November 15, 2000Date of Patent: May 13, 2008Assignee: Sun Microsystems, Inc.Inventor: Tuan Tran