Abstract: According to one embodiment of the invention, a technique is provided for relocating the contents of kernel pages in a manner similar to techniques used for relocating the contents of user pages. Before the contents of a source page are moved to a target page, for each entry of a plurality of entries that correspond to the source page, it is determined whether a mapping indicated in that entry is a mapping into kernel virtual memory address space or user virtual memory address space. If the mapping is into user virtual memory address space, then the entry is marked invalid. If the mapping is into kernel virtual memory address space, then the mapping is marked suspended. Marking an entry suspended causes processes and threads that try to access the entry's mapping to wait until the entry is no longer marked suspended. Consequently, kernel pages may be distributed among all computing system boards.

Abstract: A method for testing an intent log for a file system that includes creating a first file system, issuing a command to freeze the first file system, performing a plurality of commands on the first file system to obtain a plurality of deltas, wherein each of the plurality of deltas is stored in the intent log and is not committed to the first file system, copying the first file system to obtain a second file system, committing each of the plurality of deltas in the intent log to the second file system, unfreezing the first file system and committing each of the deltas in the intent log to the first file system, and comparing the first file system, after committing each of the deltas in the intent log, to the second file system to determine whether the intent log is valid.

Abstract: A switch contains a first semiconductor die, which is configured to receive signals on a plurality of input ports and to output the signals on a plurality of output ports. The first semiconductor die is further configured to selectively couple the signals between the input and output ports using a plurality of switching elements in accordance with a set of control signals, which correspond to a configuration of the switch. During this process, a plurality of proximity connectors, proximate to a surface of the semiconductor die, are configured to communicate the signals by capacitive coupling.

Abstract: A processor including a large register file utilizes a dirty bit storage coupled to the register file and a dirty bit logic that controls resetting of the dirty bit storage. The dirty bit logic determines whether a register or group of registers in the register file has been written since the process was loaded or the context was last restored and, if written generates a value in the dirty bit storage that designates the written condition of the register or group of registers. When the context is next saved, the dirty bit logic saves a particular register or group of registers when the dirty bit storage indicates that a register or group of registers was written. If the register or group of registers was not written, the context is switched without saving the register or group of registers. The dirty bit storage is initialized when a process is loaded or the context changes.

Abstract: A resource adapter may include modular system management interface for providing an interface between server-provided management services and back-end systems. Enterprise servers may provide management services and may host application components implementing business logic. Back-end systems may provide resources to the application components. The servers may provide services to the back-end systems to enhance efficiency, scalability, and security. Resource adapters interfacing these systems may include service adapter modules to interface between the servers and the back-end systems. For each service that a server provides to a back-end system, the corresponding resource adapter may include a service adapter module installed in the resource adapters modular system management interface. The service adapter module may isolate the code that may interact the service.

Abstract: A mechanism is disclosed for selectively providing mount information to processes running within operating system partitions. In one implementation, a non-global operating system partition is created within a global operating system environment. A file system is maintained for this non-global partition. This file system comprises zero or more mounts, and may be part of a larger, overall file system. When a process running within the non-global partition requests information pertaining to mounts, a determination is made as to which partition the process is running in. Because the process is running within the non-global partition, only selected information is provided to the process. More specifically, only information pertaining to the mounts that are within the file system maintained for the non-global partition is provided to the process. By doing so, the process is limited to viewing only those mounts that are part of the non-global partition's file system.

Abstract: A random noise generator is included in the drive circuit supplying power to a system indicator that emits optical signals. The random noise generator generates a random noise signal that is introduced into a signal input to the drive circuit so that data or covert channel information is not recoverable from the optical signals emitted by the system indicator.

Abstract: An apparatus and a method dynamically reassign resources in a coprocessor among master processors that require service from the coprocessor. The method includes each processor, in each processor cycle, keeping track of a number of resource units required for executing operations sent to the coprocessor in that processor cycle and receiving from the coprocessor a number of resource units released during the processor cycle. When the resources need to be reassigned, the coprocessor asserts a signal to the resource yielding processor to cause it to reduce its expectation of resources to zero and ceasing sending service requests to the coprocessor. The coprocessor then moves resources from the yielding processor to the resource receiving processor. Resources are then released to both processors over time to their respective adjusted resource allocations. Such resources may be the number of operations that is allowed to be executing in the coprocessor simulataneously.

Abstract: One embodiment of the present invention provides a system that facilitates storing results of resolvable branches during speculative execution, and then using the results to predict the same branches during non-speculative execution. During operation, the system executes code within a processor. Upon encountering a stall condition, the system speculatively executes the code from the point of the stall, without committing results of the speculative execution to the architectural state of the processor. Upon encountering a branch instruction that is resolved during speculative execution, the system stores the result of the resolved branch in a branch queue, so that the result can be subsequently used to predict the branch during non-speculative execution.

Abstract: Synchronized register renaming between a master processor and a coprocessor that receives operations from the master enables efficient implementation of register renaming and operation execution in the processors. An ideal and an external register allocation map are implemented in the coprocessor. When registers are no longer allocated according to the ideal allocation map and the registers are currently allocated according to the external allocation map, the registers are deallocated in the external map and the number of freed registers is reported to the master. The master increments a free register credit count accordingly, and decrements the credit count by one for each operation issued to the coprocessor. An operation is not issued to the coprocessor unless at least a register is free according to the credit count. The master also throttles coprocessor operation issue based on a credit count corresponding to free scheduler entries available in the coprocessor.

Abstract: A computer readable medium comprising software instructions for purchasing units, wherein the software instructions, when executed by a processor, enable a system including the processor to receive a request for an initial trial unit from a user, receive a request to purchase the initial trial unit from the user, complete the purchase of the initial trial unit using a first financial incentive, wherein the purchase of the initial trial unit is completed within an initial unit conversion period, provide, to the user, a second financial incentive to purchase at least one conversion unit after the completion of the purchase of the first unit, receive a request to purchase the at least one conversion unit, and complete the purchase of the at least one conversion unit using the second financial incentive, wherein the purchase of the second conversion unit is completed within a total promotion period.

Abstract: A processor employing device-specific memory address translation. In one embodiment, a processor may include a device interface configured to receive a memory access request from an input/output (I/O) device, where the request specifies a virtual memory address and a first requestor identifier (ID) that identifies the I/O device. The processor may also include an I/O memory management unit coupled to the device interface and configured to determine whether a virtual-to-physical memory address translation corresponding to the virtual memory address is stored within an I/O memory translation buffer. The I/O memory management unit may be further configured to determine whether a second requestor ID stored within the I/O memory translation buffer and corresponding to the memory address translation matches the first requestor ID. If the first and second requestor IDs do not match, the I/O memory management unit may disallow the memory access request and to signal an error condition.

Abstract: A method and system for managing events associated with either the client or the server using a controller framework includes initiating a request at a client. The request triggers an event that is processed using a client controller on the client. The client controller registers the event on the client, forwards the event to a server controller on a server, polls the server controller on the server periodically for information related to the event and retrieves notifications in response to the request or upon a poll. The client controller communicates with the server controller using asynchronous communication. The response retrieved by the client controller is loaded onto the browser of the client dynamically and rendered at the client as and when notifications are received from the server.

Abstract: A multi-stride prefetcher includes a recurring prefetch table that in turn includes a stream table and an index table. The stream table includes a valid field and a tag field. The stream table also includes a thread number field to help support multi-threaded processor cores. The tag field stores a tag from an address associated with a cache miss. The index table includes fields for storing information characterizing a state machine. The fields include a learning bit. The multi-stride prefetcher prefetches data into a cache for a plurality of streams of cache misses, each stream having a plurality of strides.

Abstract: A mechanism is disclosed for assigning repeaters to signal paths in an integrated circuit design. The mechanism involves reserving, in a first metal layer of the integrated circuit design, metal tracks for routing signals. Access points to a plurality of repeaters are reserved in a second metal layer of the integrated circuit design. Each access point is associated with a particular repeater. The design may have other layers between the second metal layer and a region reserved for the repeaters. The number of repeaters may be based on the number of metal tracks that are available to route signals through the first region. Signal paths are assigned routes that comprise at least a portion of one or more of the metal tracks. A route from signal paths requiring a repeater to access points to a particular repeater is determined. Thus, the signal paths are assigned to a repeater.

Abstract: A chip multithreading processor schedules and assigns threads to its processing cores dependent on estimated miss rates in a shared cache memory of the threads. A cache miss rate of a thread is estimated by measuring cache miss rates of one or more groups of executing threads, where at least one of the groups includes the thread of interest. Using a determined estimated cache miss rate of the thread, the thread is scheduled with other threads to achieve a relatively low cache miss rate in the shared cache memory.

Abstract: Method and apparatus for dynamically and adaptively alternating encodings, protocols, and/or transports in remoting system clients. Embodiments may provide a mechanism or mechanisms to isolate encoding, protocol, and/or transport changes in remoting system clients. In a remoting system, a server may make its service(s) available via multiple encoding, protocol and transport (EPT) combinations. One embodiment may provide a mechanism that enables a remoting system client to select an EPT combination for sending messages to a server, to have that choice drive the creation of objects and/or interface instances on the remoting system client used in the message exchange, and to switch to a different EPT combination on the remoting system client if necessary or desired. Embodiments may be used in all types of remoting systems and/or in other computing environments including, but not limited to, peer-to-peer environments.

Abstract: A method for obtaining a capability of a network interface card (NIC). The method includes sending a first data link provider interface (DLPI) request to the NIC and sending a DLPI acknowledgement to an operating system, where the DLPI acknowledgement includes the capability of the NIC. The method further includes enabling the capability on the operating system and establishing a direct communication channel between the NIC and the operating system using the capability.

Abstract: A system and method for mapping outbound communications (e.g., encapsulated Ethernet packets) from InfiniBand queue pairs (QP) and/or virtual lanes (VL) to ports through which they are to be transmitted to an external communication system. A memory is shared between the InfiniBand receive side and transmit side. A shared control structure facilitates management of a linked list for each queue pair. A linked list is composed of entries in the control structure; each entry stores a value identifying the next control entry in the list and a memory bucket associated with the entry. Each queue pair terminating has a head pointer identifying the first control entry and memory bucket, and a tail pointer identifying the last control entry and memory bucket of a linked list. When a communication is reassembled, pointers defining a sub-list comprising the communication are passed to a network transmit module.

Abstract: One embodiment of the present invention provides a system that generates a synthetic workload to test power utilization in a computer system. During operation, the system monitors power utilization of a reference computer system while the reference computer system executes a workload-of interest, wherein the monitoring process produces a power profile. Next, the system determines characteristics of the workload-of-interest from the power profile. Finally, the system uses the determined characteristics to construct the synthetic workload, wherein the synthetic workload has similar power utilization to the workload-of-interest.