Abstract: A method for maximizing revenue generated from a plurality of service level agreements (SLAs) that includes receiving a first subset of the plurality of SLAs for executing a first plurality of jobs, wherein each SLA in the first subset specifies a first maximum requested delay that is greater than an initial minimum offered delay, and wherein a price of each SLA in the first subset is defined by the maximum requested delay and a price/delay function, calculating a first expected revenue from executing the first subset, and optimizing a second subset of the plurality of SLAs by replacing the initial minimum offered delay on the initial price/delay function with a new minimum offered delay based on the expected revenue, wherein each SLA in the second subset specifies a second maximum requested delay that is greater than the new minimum offered delay.

Abstract: A system may include a plurality of nodes. Each node may include one or more active devices coupled to one or more memory subsystems. An active device included in one of the nodes includes a memory management unit configured to receive a virtual address generated within that active device and to responsively output a global address identifying a coherency unit. A portion of the global address identifies a translation function. A memory subsystem included in the node is configured to perform the translation function identified by the portion of the global address on an additional portion of the global address in order to obtain a local physical address of the coherency unit. Each active device included in the node is configured to use the portion of the global address identifying the translation function when determining whether a local copy of the coherency unit is currently stored in a cache associated with that active device.

Abstract: Methods and systems consistent with the present invention allow a program designer to conveniently specify and support watchdog checking of a program under development. The resulting programs are more robust than programs developed without watchdog support. The method and systems provide a convenient, automated mechanism for adding watchdog support to a program. Thus, a developer need not incur the substantial time and effort costs that would be associated with manually designing and configuring separate watchdog programs. Rather, the methods and systems provide substantial assistance to the developer in designing a robust program.

Abstract: A cache memory with improved cache-miss performance is implemented by providing cache-miss data from system memory directly to its requester. One embodiment of the invention operates as a texture cache in a graphics system. The graphics system comprises a system memory that stores texture data, coupled to a texture cache memory, which is coupled to at least one requester. The texture cache memory is divided into a cache tags unit and a data cache unit. The data cache unit is configured to receive at least two cache address inputs, and has at least two data output ports each coupled to a respective first input of a respective multiplexer. A respective second input of each multiplexer is configured to receive cache-miss data from the system memory. The select input of each multiplexer is configured to receive a respective hit/miss indicator signal associated with the respective cache address input. In case of a cache-miss, cache-miss data from system memory bypasses the data cache unit and is output directly.

Abstract: A memory interface comprising a first data input for receiving a data line to be stored in memory, a bad chip register containing a bad chip value for identifying a bad memory chip of a memory device to be used with the memory interface, and a write shift logic circuit receiving the data line from the first data input. The data line contains a plurality of data bits and a plurality of check bits, the check bits being logically appended to one end of the data bits. The write shift logic, in response to the bad chip value, causes a portion of the data line to be shifted toward the one end of the bad memory chip.

Abstract: One embodiment of the present invention provides a system that manages an LRU list such that the rank, or position, of data records in the sequence can be determined efficiently. The system initializes an index field in each record to the record's initial rank. When a record is accessed, the system moves it to the beginning of the LRU list and appends the value of the record's index field to a “change list.” The system then sets the record's index field to zero. The change list effectively tracks the records accessed since initialization, and combined with the records' index fields can be used to efficiently compute the rank of any record in the list. This ability to efficiently compute the rank of the data record in the LRU list reduces the frequency with which the computationally-expensive initialization operation must be executed on the LRU list.

Abstract: An invention is provided for displaying two-dimensional data on small screen devices. The invention includes providing a first data set display section on a screen, which is capable of presenting a list of entries in a first data set. In addition, a second data set display section is provided on the screen. The second data set display section is capable of presenting a particular entry from a second data set associated with a selected entry from the first data set. In operation, a new entry from the second data set is presented in the second data set display section in response to receiving a navigation command related to the second data set. The new entry is associated with the selected entry from the first data set.

Abstract: A portable storage device, for example a secure smart card, contains network identification information for a processing unit that is connectable to a data communications network, which processing unit includes a device reader for reading the portable storage device. The portable storage device includes storage and an access controller. The storage holds a network identity for the processing unit and at least one encryption key. The access controller is operable to control access to the storage by implementing key-key encryption. An embodiment of the invention thus provides a medium not only for storing a network identity for processing unit, but also for other secure information such as an encryption key associated therewith.

Abstract: One embodiment of the present invention provides a system that uses a single built-in-self-test (BIST) engine to test multiple on-chip memory structures. During chip-test or power-on-self-test in the system, the BIST engine tests multiple on-chip memory structures which reside at different locations on the chip. During this testing process, the BIST engine performs at-speed data-parallel testing operations for the multiple on-chip memory structures. In doing so, the BIST engine communicates with the multiple on-chip memory structures through data paths which are used for other purposes during normal operation of the chip, but which are used for communications between the BIST engine and the multiple on-chip memory structures during the testing process.

Abstract: In a client-server architecture, data transmission performance enhancing features are described, including a color quality approach and a packet shaping approach. A method includes a color quality data transformation including: selecting a quality level to apply to a set of image data having a number of significant color bits defining an initial number of possible colors; applying a pixel mask to the set of image data, the initial number of possible colors reduced to a smaller number of possible colors as a function of the quality level; loading the set of image data into an output buffer; and sending the set of image data from the output buffer to a display engine.

Abstract: One embodiment of the present invention provides a system that monitors system-calls to identify runaway processes within a computer system. First, the system monitors system-calls on the computer system during runtime, to generate a trace of system-calls made. Then, the system analyzes the trace to detect runaway processes.

Abstract: A method and apparatus for performing a store-to-instruction-space instruction are provided. A unique opcode indicates that a data value is to be written to an instruction space in main memory. The instruction is received and executed. After the instruction space is modified to contain the data value, further processing is performed to ensure coherence between main memory and an instruction cache.

Abstract: A method for obtaining a quorum vote by a first node using a Universal Serial Bus (USB) quorum cable, wherein the USB quorum cable comprises a first end connected to a first node and a second end connected to a second node, including determining whether the USB quorum cable is reserved by the second node by querying a memory located in the USB quorum cable, if the USB quorum cable is not reserved by the second node attempting to reserve the USB quorum cable, determining whether the attempt to reserve the USB quorum cable was successful, and obtaining the quorum vote by the first node, if the attempt to reserve the USB quorum cable is successful.

Abstract: A system may include a node coupled to an additional node by an inter-node network. The node may include several active devices, an interface to the inter-node network, and an address network configured to convey address packets between the interface and the active devices. One of the active devices is configured to send an address packet on the address network to initiate a transaction to gain an access right to a coherency unit. In response to the address packet, the interface is configured to send data corresponding to the coherency unit to the active device if no other active device in the node has an ownership responsibility for the coherency unit and the coherency unit is in a modified global access state in the node.

Abstract: An address translation unit is provided for use in a computer system. The unit contains a set of page table entries for mapping from a virtual address to a packet address. Each page table entry corresponds to one page of virtual memory, and typically includes one or more specifiers. Each specifier relates to a different portion of the page, and maps from that portion of the page to a corresponding range of packet addresses. Accordingly, the unit allows for address translation to be performed with a sub-page granularity.

Abstract: Embodiments of a switch are described. This switch includes input ports configured to receive signals (which include data) and output ports configured to output the signals. In addition, the switch includes switching elements and a flow-control mechanism, which is configured to provide flow-control information associated with the data to the switching elements via an optical control path. These switching elements are configured to selectively couple the input ports to the output ports based on the flow-control information. Furthermore, a given switching element in the switching elements is coupled to a given input port and a given output port via electrical signal paths that are configured to use proximity communication to communicate the data.

Abstract: A system and method for describing multiple packets to a communication module or device without requiring descriptors for each packet. A device driver for the communication apparatus receives a set of packet headers and a set of packet payloads from an upper layer protocol. The headers may be received in a header buffer, and the payloads may be received in a separate data buffer. Or, the packets may be received, in assembled form, in a single buffer. The device driver configures a single descriptor to describe the multiple packets to the communication apparatus. The descriptor includes base address(es) of the buffer(s) in which the headers, payloads or assembled packets are stored, and the lengths of the individual headers, payloads or assembled packets. If the buffer contents are not packed, the descriptor may also include offsets of the headers, payloads or packets.

Abstract: A PCI-Express interconnect device is provided. The device comprises: first and second upstream ports; first and second downstream ports; and a management entity. The management entity is operable to logically partition the device such that the first upstream port is operable to communicate with the first downstream port and the second upstream port is operable to communicate with the second downstream port. In one example, the management device is additionally operable to migrate the first downstream port from a partition in which the first downstream port is operable to communicate with the first upstream port into a partition in which the first downstream port is operable to communicate with the second upstream port.

Abstract: A system that detects the onset of degradation for interconnections in a component within a computer system. During operation, the system monitors inferential variables associated with the interconnections during operation of the computer system. Next, the system determines a present state of the component from the monitored inferential variables. The system then compares the present state of the component with an initial state of the component. If the comparison indicates that the interconnections in the component have reached or will reach a limited operating state (LOS), the system performs a remedial action.

Abstract: A CPU is provided with an ability to modify its operation, with respect to error correction, as a programmable feature. An error correction scheme is selected to be performed by the error correcting circuit. The compiled program may have intentionally introduced errors which are predictably corrected by the selected error correction scheme. When a program is compiled, the program is modified by the intentional insertion of errors which would result from the execution of the program. By providing error correction schema selected during program compilation, errors can be inserted in the program code, but are handled in a predictable manner by the error correction.