Abstract: A system and method for application resource utilization metering and cost allocation in a utility computing environment. In one embodiment, the system may include a computational resource, a plurality of applications configured to utilize the computational resource, a metering utility configured to measure utilization of the computational resource by a given one of the plurality of applications, and a cost model configured to allocate a first portion of a cost of the computational resource to the given application dependent upon the measured utilization of the computational resource by the given application.

Abstract: A method for creating an install program involves selecting a plurality of icons (where each of the plurality of icons represents an element of the install program), defining the install program by placing and arranging the plurality of icons onto a workspace to obtain a defined install program, and building the install program based on the defined install program.

Abstract: One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program, the system commences transactional execution of the block of instructions following the STE instruction. Changes made during this transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes.

Abstract: An interface is provided to couple an input/output device (e.g., a network interface unit) to one or more different host system buses without altering the configuration of the device (e.g., to include logic specific to the host buses). Functionality of the device (e.g., MTU size, error detection) is therefore independent of the host bus. Host bus logic for managing operation of the host bus is augmented with logic for translating between semantics of the interface and the host bus. Also, end-to-end verification of a complex ASIC in multiple configurations or environments can be performed over the interface without probing into the ASIC.

Abstract: A method and mechanism for managing operating system instances in a computing system. A computing system is configured to enable users to model and manage operating system instances. One or more defined operating system instances may be created and stored for future use. Each of the defined operating system instances may include a description of required resources. In addition, the definition of desired and/or optimal resources may be specified. In response to an attempt to realize an operating system instance, a determination is made as to whether resources allocated for the operating system instance are adequate. If the allocated resources are inadequate, further resources may be allocated. In addition, a determination may be made as to whether a standby mode is indicated for the operating system instance. If a standby mode is indicated, the operating system instance may be realized but not booted.

Abstract: A method for storing a data block, comprising compressing the data block using a first compression algorithm to obtain a compressed data block, generating a data block compression header, combining the compressed data and the data compression header to obtain a compressed data block package, storing the compressed data block package in a storage pool, obtaining a compressed data block package location, calculating a data block checksum for the compressed data block, and storing a first indirect block in the storage pool, wherein the first indirect block comprises the compressed data block package location, the data block checksum, and a compression flag.

Abstract: A method and computer program product for detecting and diagnosing errors in a generic function call and then presenting them in an error message is disclosed. A generic function call is provided for evaluation. A corresponding generic function definition containing sets of dummy arguments that define arguments signatures for associated specific functions is also provided. In a first sorting the generic function call is compared with the argument signatures to determine whether the generic function call contains errors. A second sorting is then used to determine the nature of the errors. An error message describing the nature of the errors is then generated.

Abstract: Cache logic associated with a respective one of multiple processing threads executing in parallel updates corresponding data fields of a cache to uniquely mark its contents. The marked contents represent a respective read set for a transaction. For example, at an outset of executing a transaction, a respective processing thread chooses a data value to mark contents of the cache used for producing a transaction outcome for the processing thread. Upon each read of shared data from main memory, the cache stores a copy of the data and marks it as being used during execution of the processing thread. If uniquely marked contents of a respective cache line happen to be displaced (e.g., overwritten) during execution of a processing thread, then the transaction is aborted (rather than being committed to main memory) because there is a possibility that another transaction overwrote a shared data value used during the respective transaction.

Abstract: A method for managing identification in a data communications network includes receiving a user-controlled secure storage device and enrolling the user with an authority network site. The enrolling includes providing information requested by the authority network site. The method also includes receiving user data in response to the enrolling, storing the user data in the user-controlled secure storage device, enabling the user-controlled secure storage device to release the user data and using the user data at a service provider network site to obtain a service.

Abstract: It has been discovered that preventing performance of ineffective write operations reduces demand on memory bandwidth, as well as preventing unnecessary consumption of resources. A write operation is inspected to determine whether the write operation will effectively modify the destination of the write operation (i.e., whether a net change will occur). Those ineffective write operations are not performed. Preventing performance of the write operation includes not changing contents of locations in a memory hierarchy that correspond to the destination of the write operation.

Abstract: A system for controlling contention between conflicting transactions in a transactional memory system. During operation, the system receives a request to access a cache line and then determines if the cache line is already in use by an existing transaction in a cache state that is incompatible with the request. If so, the system determines if the request is from a processor which is in a polite mode. If this is true, the system denies the request to access the cache line and continues executing the existing transaction.

Abstract: In data processing systems that use a snoopy based cache coherence protocol and which contain a read only cache memory with a bounded range of addresses, a cache line hit is detected by assuming that, if an address contained in a request falls within the bounded range, the cache line is present in the cache memory for snoop results. This is equivalent to assuming that the cache line is marked as shared when it might not be so marked.

Abstract: A memory system is disclosed. The memory system includes a memory controller coupled to one or more memory modules, at least one of the memory modules including a buffer. The memory controller is configured to convey a command to at least one of the memory modules in response to detecting that no memory requests addressed to the at least one of the memory modules have been received during a specified window of time. In response to the command, the buffer of the at least one of the memory modules is configured to enter a reduced power state. The specified window of time may be either a specified number of memory refresh intervals or buffer sync intervals. The memory controller maintains a count of memory refresh or buffer sync intervals.

Abstract: A proximity interconnect module includes a plurality of off-chip cache memories. Either disposed external to the proximity interconnect module or on the proximity interconnect module are a plurality of processors that are dependent on the plurality of off-chip cache memories for servicing requests for data. The plurality of off-chip cache memories are operatively connected to either one another or to one or more of the plurality of processors by proximity communication. Each of the plurality of off-chip cache memories may cache certain portions of the physical address space.

Abstract: A lightweight, concurrent detection mechanism avoids global thread suspension by operating during runtime with threads under examination. A particular configuration combines a dependency (“waits for”) snapshot with a progression check to determine advancement of purportedly deadlocked threads. Thread blocking is enumerated in a table or graph which denotes dependencies of threads and the corresponding resources. For identified circular dependencies, a successive transition, or progression check ratifies the potential deadlock. A transition counter corresponding to each thread is analyzed in the progression check. The transition counter is indicative of a change in state for the process in question, hence is indicative of instruction execution, an activity not performed by a blocked process. Deadlock is therefore ratified if the transition counters associated with the threads in the potential deadlock have not advanced.

Abstract: A system and method of navigating a mobile device display includes highlighting a first icon in a main portion of the mobile device display. The main portion is traversed to a tertiary tray. The tertiary tray includes a second icon. The second icon is highlighted. A single navigation key is used to traverse the main portion and to highlight the second icon.

Abstract: The present invention generally relates to synchronization of multiple threads in an out-of-order microprocessor utilizing the insertion of a trap. In one embodiment, while synchronizing multiple running threads, an instruction within a first running thread is identified. Upon identification of this instruction, a trap is inserted into a second running thread. All instructions within the instructional pipeline that are scheduled for execution prior to this trapped instruction must retire before the subsequent execution of the synchronizing instruction. Following the execution of the synchronizing instruction, all instructions within the instruction pipeline slated for execution after the trapped instruction in the remaining threads are flushed and refetched.

Abstract: A method for synchronized renaming between a master processor and a coprocessor includes sending from the master processor an operation for execution by the coprocessor along with an identifier, at the coprocessor, renaming the operation for execution, including assigning a resource and associating the resource with the identifier, and at a subsequent time, sending the identifier from the master processor to the coprocessor to be used in conjunction with the execution of the renamed operation.

Abstract: A system and method for storing data in a virtual file system using write once read many (WORM) protection includes a WORM server in communication with one or more storage devices and a controller in communication with the WORM server. A first time stamping process for creating a first time stamp for a data object based on instructions applied by the controller for storage on the WORM server. A second time stamping process for creating a second time stamp for the data object for storage on the WORM server. The second time stamping process creates the second time stamp for the data object and first time stamp to ensure the integrity of the data object stored on the system.

Abstract: Methods and apparatus for representing application dependencies are disclosed. A software application is executed according to an associated state machine. A set of dependencies relationship rules indicates dependencies of a set of software applications upon the software application based upon the state of the software application. The set of dependencies relationship rules may be represented by a dependencies graph, where the software application and the set of software applications are each represented by a dependency node in the dependencies graph and each line connecting the software application with one of the set of software applications corresponds to one or more dependency statements indicating a change in state in one of the set of software applications in response to a change in state of the software application.