Abstract: Dynamic logical mapping (“DLM”) provides a virtual layer interposed between a host and a data storage library. Residing on the library, DLM creates a data storage map that records and manages the relationship between a storage cartridge's physical address and that cartridge's mapping to a logical address. During runtime of the data storage library, DLM manages the physical to logical address mapping of each storage cartridge so as to optimize efficiency and speed of the data storage library.

Abstract: Apparatus and processes, including computer implemented processes, for managing exceptions throwable during execution of methods in one or more classes by a machine. Each method includes an exception handler array defining exception handlers associated with the method. The method includes combining the exception handler arrays for all methods into a single exception handler table.

Abstract: A circuit for accessing an associative cache is provided. The circuit includes data selection circuitry and an outcome parallel processing circuit both in communication with the associative cache. The outcome parallel processing circuit is configured to determine whether an accessing of data from the associative cache is one of a cache hit, a cache miss, or a cache mispredict. The circuit further includes a memory in communication with the data selection circuitry and the outcome parallel processing circuit. The memory is configured to store a bank select table, whereby the bank select table is configured to include entries that define a selection of one of a plurality of banks of the associative cache from which to output data. Methods for accessing the associative cache are also described.

Abstract: A system that suppresses duplicative prefetches for branch target cache lines. During operation, the system fetches a first cache line into in a fetch buffer. The system then prefetches a second cache line, which immediately follows the first cache line, into the fetch buffer. If a control transfer instruction in the first cache line has a target instruction which is located in the second cache line, the system determines if the control transfer instruction is also located at the end of the first cache line so that a corresponding delay slot for the control transfer instruction is located at the beginning of the second cache line. If so, the system suppresses a subsequent prefetch for a target cache line containing the target instruction because the target instruction is located in the second cache line which has already been prefetched.

Abstract: Method and apparatus for the self-organization of nodes into groups in network computing environments. Embodiments may provide the ability to deploy nodes on a network, and to allow the nodes to organize into groups without human intervention. In one embodiment, a node may broadcast a query looking for a master node for the group. If the query produces no responses, the node may self-elect as the master node for the group and the node may broadcast its presence as the master node. If two or more nodes self-elect as master nodes, the nodes may negotiate to determine which node will be the master node. If the master node becomes unavailable, the remaining nodes in the group may elect a new master node. Some embodiments may be implemented on a peer-to-peer platform, such as the JXTA peer-to-peer platform, which may allow the scope of the group to span subnetworks and networks.

Abstract: A mechanism is disclosed for logging system messages in an operating system environment that has been partitioned into a global zone and one or more non-global zones. Each of the zones is associated with a separate log device node. A separate syslogd process executes in association with each zone. Each zone is associated with a separate virtual file system that contains a separate log file. Application processes executing in association with a zone can send messages to the log device node for that zone. The syslogd process executing in association with a zone reads messages from that zone's log device and writes at least some of the messages into that zone's log file. Consequently, the system logging ability is maintained in all of the zones, while isolating the processes and data in each zone from the processes and data in each other non-global zone.

Abstract: A client-server system for downloading a data file from a server to a client with real time verification. The system including a server. The server including a data file, and a verification file. The verification file containing first error detection data associated with the data file. The system also including a client which communicates with the server through a network. The client including a download manager for downloading the data file from the server to the client. When the download manager downloads at least a portion of the data file, the download manager generates second error detection data associated with the data file and compares the first and second error detection data to determine if errors occurred in the data file.

Abstract: In one embodiment, a processor comprises a branch prediction array, an index generator coupled to the branch prediction array, and a control unit coupled to the index generator. The branch prediction array is configured to store a plurality of branch predictions for conditional branches. The index generator is configured to generate an index to the branch prediction array responsive to at least a portion of a fetch address corresponding to a fetch request that is at a first pipeline stage of the processor and further responsive to a branch history. The control unit is configured to update the branch history responsive to a first fetch request at the first pipeline stage and to defer the update for a second fetch request to a second pipeline stage subsequent to the first pipeline stage.

Abstract: A system and method for detecting and preventing race conditions in a circuit is provided. The system includes a first memory element for receiving a data stream. The system further includes a plurality of additional memory elements for directly receiving an output of the data stream from the first memory element. Delay elements are defined between the first memory element and the plurality of additional memory elements other than a second memory element, so that each delay element between the first memory element and the plurality of additional memory elements other than the second memory element are combined to define a sum delay. A plurality of comparators are connected to the plurality of memory elements such that each comparator being configured to compare an input to the first memory element and an output of each of the plurality of additional memory elements.

Abstract: Embodiments of an encoding circuit to communicate a sequence of words are described. This encoding circuit includes an encoding module that is configured to receive a first sequence of words and to generate a DC-balanced second sequence of words based on the first sequence of words, where communicating the second sequence of words consumes less energy than communicating a third sequence of words that includes words in the first sequence of words alternating with words in the inverse of the first sequence of words. In addition, the second sequence of words includes substantially twice as many words as the first sequence of words.

Abstract: Modular multiplication of two elements X(t) and Y(t), over GF(2), where m is a field degree, may utilize field degree to determine, at least in part, the number of iterations. An extra shift operation may be employed when the number of iterations is reduced. Modular multiplication of two elements X(t) and Y(t), over GF(2), may include a shared reduction circuit utilized during multiplication and reduction. In addition, a modular multiplication of binary polynomials X(t) and Y(t), over GF(2), may utilize the Karatsuba algorithm, e.g., by recursively splitting up a multiplication into smaller operands determined according to the Karatsuba algorithm.

Abstract: A method for cooling electronic equipment. The method including propagating air through a first electronic component of the electronic equipment into a first enclosed area, where propagating the air through the first electronic component cools the first electronic component, circulating a refrigerant in a cooling loop, where the cooling loop comprises a heat exchanger, and propagating the air out of the first enclosed area by passing through the heat exchanger into a second enclosed area, where the air is cooled by passing through the heat exchanger.

Abstract: Various embodiments of mechanisms for bridging data representation language messaging based distributed computing environments to foreign environments are described. A device proxy may implement a device protocol and a distributed computing environment protocol to bridge devices into the distributed computing environment. A client proxy is described that implements the distributed computing environment protocol on behalf of a foreign client such as a browser. A service proxy is described that implements the distributed computing environment protocol on behalf of a foreign service. A transport proxy is described that routes data representation language messages between two different message transports. A distributed computing environment client proxy may allow distributed computing environment clients to access Remote Method Invocation (RMI)-based environment services. An RMI-based environment client proxy may allow RMI-based environment clients to access distributed computing environment services.

Abstract: An estimate of the throughput of a multi-threaded processor based on measured miss rates of a cache memory associated with the processor is adjusted to account for cache miss processing delays due to memory bus access contention. In particular, the throughput calculated from the cache memory miss rates is initially calculated assuming that a memory bus between the cache memory and main memory has infinite bandwidth, this throughput estimate is used to estimate a request cycle time between memory access attempts for a typical thread. The request cycle time, in turn, is used to determine a memory bus access delay that is then used to adjust the initial processor throughput estimate. The adjusted estimate can be used for thread scheduling in a multiprocessor system.

Abstract: A dynamic prediction is made whether a load instruction will miss a cache. Data is prefetched for the load instruction when a cache miss is predicted. Thus, the prefetch is only performed if a trigger event correlated with a cache miss for that load instruction is detected. This selective execution of the prefetches for a particular load instruction improves processor utilization and performance.

Abstract: One embodiment of the present invention provides a system that facilitates optimizing computer program performance by using steered execution. The system operates by first receiving source code for a computer program, and then compiling a portion of this source code with a first set of optimizations to generate a first compiled portion. The system also compiles the same portion of the source code with a second set of optimizations to generate a second compiled portion. Remaining source code is compiled to generate a third compiled portion. Additionally, a rule is generated for selecting between the first compiled portion and the second compiled portion. Finally, the first compiled portion, the second compiled portion, the third compiled portion, and the rule are combined into an executable output file.

Abstract: Methods and systems for protecting object identity in an object-oriented programming language. An object from a class for protecting object identity is instantiated in memory. The object includes a first method that determines whether two object values are equal, and a second method that overrides an identity method associated with a superclass of the object by invoking the first method, the identity method for determining the identity of two objects. The object is immediately locked in response to the instantiating, so that the identity of the locked object is protected from threads that attempt to synchronize on the locked object.

Abstract: One embodiment of the present invention provides a system that supports low-latency session-mobility for an ultra-thin-client. During system operation, an ultra-thin-client sends a location-identifier to a Connection Assignment Server (CAS), which facilitates communication with a user-interface (UI) server, wherein the location-identifier specifies the current location of the ultra-thin-client. Next, the ultra-thin-client receives the address of a local UI-server from the CAS, wherein the CAS selects the local UI-server based on the location-identifier. The ultra-thin-client then sends a user-session identifier to the local UI-server. This allows the local UI-server to retrieve a user-session-image for a user-session from a user-session-image repository. Note that, before moving to the current location, the ultra-thin-client was previously communicating with a remote UI-server, which stored the user-session-image in the user-session-image repository.

Abstract: A method for processing a chain of packets involving obtaining the chain of packets from a network, obtaining destination information from a first packet in the chain of packets, determining whether destination information of the first packet matches destination information of a second packet in the chain of packets, aggregating the first packet and the second packet to obtain an aggregated chain of packets, if destination information of the second packet matches the destination information of the first packet, hashing destination information to obtain a hash value, and forwarding the aggregated chain of packets to at least one client using the hash value.

Abstract: A design of an integrated circuit is first verified using directed and/or random test cases. For a cover directive not covered by the directed and/or random test cases, a property is created, where a simulation trace that causes the property to fail covers the cover directive. Thereafter, the property is evaluated, and dependent on the evaluation, the simulation trace is dumped and stored for subsequent exercising of the cover directive.