Abstract: Reference updating in a sliding compaction garbage collector may involve maintaining, for each logical region of the heap to be compacted, values that represent the range of addresses referenced by individual regions of the heap. For example, a highest-referenced address (HRA) represents the maximum address referenced by any object references in the respective region. Similarly, a lowest-reference address (LRA) represents the minimum address referenced by a region. When updating references during compaction, if the HRA and/or LRA for a particular region indicate that all references within the region point to addresses within a region of memory that will not be relocated during compaction, such as a dense prefix, the references with the particular region need not be updated. Maintaining HRAs and/or LRAs for region of heap memory may simplify determining whether or not references within individual regions require updating.

Abstract: A system to execute an application comprises a cluster of a plurality of application server nodes. A particular one or more of the application server nodes has residing thereon at least one container that contains business logic for the application. The particular one or more of the application server nodes is configured to maintain self-timing information for use to schedule execution of the business logic contained by the at least one container residing on the particular one or more application server nodes. Also, at least one of the other application server nodes is configured to maintain backup timing information for the particular one or more of the application server nodes, from which the self-timing information maintained by the particular one or more of the application server nodes can be derived.

Abstract: In one embodiment, a system comprises a source configured to provide data and a source error correction code (ECC) generated according to a source ECC scheme; a circuit comprising an ECC transform unit configured to generate a target ECC from the data, detect an error in the data responsive to the source ECC, and correct the error in the data, wherein the target ECC is generated according to a target ECC scheme different from the source ECC scheme, and wherein the ECC transform unit is configured to continuously protect the data with at least one of the source ECC and the target ECC; and a target coupled to receive the data and the target ECC from the circuit.

Abstract: A mask is first generated in a general-purpose integer register. The mask is generated by executing a single instruction multiple data (SIMD) instruction on a plurality of operands stored in a plurality of registers and by writing the result to the general-purpose integer register. Next, a conditional-move mask is generated in a register using the mask, and then the conditional-move mask is used in selecting operands from the plurality of operands to generate a result in another register.

Abstract: One embodiment of the present invention provides a system that determines fan speeds for a set of fans in a computer system. During operation, the system receives time-series data collected by a vibration transducer associated with the computer system, wherein the vibration transducer is configured to record mechanical vibrations from the set of fans. Next, the system performs a spectral analysis on the time-series data to obtain frequency peaks associated with fan speeds for individual fans in the set of fans. The system then identifies fan speeds for the individual fans in the set of fans from the frequency peaks.

Abstract: Embodiments of the present invention implement virtual transactional memory using cache line marking. The system starts by executing a starvation-avoiding transaction for a thread. While executing the starvation-avoiding transaction, the system places starvation-avoiding load-marks on cache lines which are loaded from and places starvation-avoiding store-marks on cache lines which are stored to. Next, while swapping a page out of a memory and to a disk during the starvation-avoiding transaction, the system determines if one or more cache lines in the page have a starvation-avoiding load-mark or a starvation-avoiding store-mark. If so, upon swapping the page into the memory from the disk, the system places a starvation-avoiding load-mark on each cache line that had a starvation-avoiding load-mark and places a starvation-avoiding store-mark on each cache line that had a starvation-avoiding store-mark.

Abstract: Some embodiments of the present invention provide a system that automatically revokes data on a portable computing device. During operation, the system uses a key K1 to encrypt data on the portable computing device. The system then attempts verify that the portable computing device is secure. If the attempt to verify that the portable computing device is secure fails, the system causes K1 to be removed from the portable computing device.

Abstract: One embodiment of the present invention provides a system for troubleshooting a computer system. During operation, the system receives an identifier for a suspect computer system, which is suspected of operating abnormally. The system also receives an identifier for a normal computer system, which is operating normally. Next, the system automatically sends a command to be executed to both the suspect computer system and to the normal computer system. The system subsequently receives a response to the command from both the suspect computer system and the normal computer system and compares the responses to determine differences in behavior between the suspect computer system and the normal computer system.

Abstract: A method for deploying a directory server that includes receiving a new version of the directory server on a server to replace a prior version of the directory server, wherein the new version of the directory server uses a new version of an access policy and the prior directory server uses a prior version of the access policy, and configuring the new version of the directory server to use both the prior version of access policy and the new version of the access policy, wherein the new version of the directory server maintains compatibility between the new version of the access policy and the prior version of the access policy.

Abstract: A parallel iterative decoding system interposed between a network interface and a block memory matrix receives encoded data and both stores the data in a First-In-First-Out (“FIFO”) memory block and processes it through a timing recovery engine. The timing recovery engine delivers to an iterative decoder synchronized data samples and detects cycle slip. The iterative decoder thereafter performs a predetermined number of iterations to decode the data. Responsive to encoded data failing to converge after the predetermined number of iterations, the encoded data is communicated from the FIFO memory to an auxiliary decoder module. The auxiliary iterative error correction code decoder performs a second predetermined number of iterations to decode the data wherein the number of iterations performed by the auxiliary iterative error correction code decoder is greater than the primary iterative error correction code decoder.

Abstract: An apparatus and method to support pipelining of variable-latency instructions in a multithreaded processor. In one embodiment, a processor may include instruction fetch logic configured to issue a first and a second instruction from different ones of a plurality of threads during successive cycles. The processor may also include first and second execution units respectively configured to execute shorter-latency and longer-latency instructions and to respectively write shorter-latency or longer-latency instruction results to a result write port during a first or second writeback stage. The first writeback stage may occur a fewer number of cycles after instruction issue than the second writeback stage. The instruction fetch logic may be further configured to guarantee result write port access by the second execution unit during the second writeback stage by preventing the shorter-latency instruction from issuing during a cycle for which the first writeback stage collides with the second writeback stage.

Abstract: A system that reduces the size of a design data set. During this design data set reduction operation, the system computes a decision boundary which separates a first group of data patterns in a training data set from a second group of data patterns in the training data set. For each data pattern in the training data set, the system determines if removing the data pattern from the training data set substantially affects the resulting decision boundary. If so, the system marks the data pattern as a key pattern. The system then removes all data patterns that are not marked as key patterns to produce a reduced training data set which represents the decision boundary.

Abstract: In an apparatus and method for providing device sharing, a first plurality of upstream ports are each connectable to a respective host and at least one downstream port is connectable to a device. A virtual port is defined that is associated a routing table to effect device virtualization by redirection of information packets received by the virtual port.

Abstract: A system for mapping memory of a computer system includes a sorter, a partitioner, and a mapper. The sorter sorts a physical memory space to obtain a sorted virtual memory space, where the physical memory space includes a plurality of memory patterns, wherein each of the plurality of memory patterns is associated with a physical device and includes at least one memory block, wherein the at least one memory block is contiguous and addressable, and the plurality of memory patterns are arranged based on a predefined number of occurrences of each memory pattern, size of contiguous memory address ranges in each of the plurality of memory patterns, size of contiguous memory address ranges in each of the plurality of memory patterns, and arrangement of contiguous address ranges in each of the plurality of memory patterns.

Abstract: A generic conversion framework that allows developers to develop custom plug-in conversion algorithms and/or merge algorithms (referred to as pluggable modules). In one embodiment, document merging may be split into two processes including a document differencing process and a document merging process. The converter, differencing and merger processes may be implemented as separate pluggable modules, allowing multiple, independent passes of implementations of the differencing process and the merge process. The framework may accept document converter plug-in modules, merger plug-in modules and/or differencing plug-in modules to be added, updated or replaced as needed. In one embodiment, the modules may be plugged into the framework dynamically at runtime. In one embodiment, a plug-in module of one type may be used with two or more different modules of another type.

Abstract: Web services interface policy constraints may be specified in a policy constraints language and policy processing, such as generating an intersection policy of two policies may be automated by a policy-processing engine. A policy constraint may be a specification of a value, range of values, or set of values that a particular requirement or offering is allowed to have. Hierarchies of requirements and/or offerings may also be expressed and matched such that a more specific case of a requirement or offering may be matched against a more general case of the same requirement or offering. Also, preferences among vocabulary items, vocabulary item values, policy constraints, and other elements of a policy may be specified and automatically determined by a policy-processing engine. Automated matching of consumer requirements against provider offerings may allow a policy-processing engine to process policies with specifications of requirements or offerings from any domain-specific schema.

Abstract: A method is provided for obtaining data to be used in evaluating performance of a computer processor. More specifically, the method provides for efficiently obtaining traces from an application program for use in a simulation of a computer processor. The method uses both an original code defining the application program and an instrumented version of the original code (“instrumented code”). The method includes apportioning a total time of execution of the application program between the original code and the instrumented code. Transition of execution between the original and instrumented codes is conducted through either modification of function calls or through consultation with a mapping of instruction address correspondences between the original and instrumented codes.

Abstract: A system and method for storing error correction check words in computer memory modules. Check bits stored within a given word line in a dynamic random access memory (DRAM) chip are assigned to different check words. By assigning check bits to check words in this manner, multi-bit soft errors resulting from the failure of a word line will appear as single-bit errors to an error correction subsystem.

Abstract: A gateway between client manager applications and an enterprise manager may be provided to manage various networked objects. In one embodiment, CORBA-based TMN manager applications may be communicatively coupled to a CORBA Object Request Broker (ORB) and may be operable to send Interface Definition Language (IDL) requests to, and receive IDL responses and CORBA events from, managed objects through the CORBA ORB. The client manager may first be authenticated to the gateway by username and password, or other validation information associated with the client manager, which may be represented in a user profile. Once the initial client authentication is accomplished, the gateway may provide object-level access control between manager applications and managed objects at an individual object level so that one of the managers is granted access to one of the managed objects while being prevented from interfacing with a different one of the managed objects.

Abstract: A method for executing input/output (I/O) operations based on priority involves receiving a first I/O request for a unit of data, receiving a second I/O request for the same unit of data, determining a priority of the first I/O request and a priority of the second I/O request, and executing the first I/O request based on priority, where the first I/O request is executed based on the higher of the priority of the first I/O request and the priority of the second I/O request.