Abstract: A method for inserting repeaters into an integrated circuit synthesis is provided. The method initiates with identifying possible repeater insertion locations along a signal routing pathway within an integrated circuit design. The possible repeater insertion locations are organized in a tree enabling bottom-up traversal. A set of solutions for each of the insertion locations is generated while traversing the tree in a first direction and the set of solutions is organized in a first and a second set, the first set ordered by a late mode capacitive load and the second set order by an early mode capacitive load. A computer readable medium including program instructions representing the method operations and a system are also included.

Abstract: The present application describes techniques for determining maximum acceptable modeled load latency (e.g., a model number of clock cycles required between the time a load issues and the time its use can issue) for instruction scheduling which uses less compile time, on the order of log2 (Maximum load latency—Minimum load latency). Typically, during instruction scheduling, register pressure is monotonically non-decreasing with respect to the scheduled load latency. Therefore, in some embodiments, a hierarchical search method is used to determine the acceptable schedule with the largest modeled load latency. According to an embodiment, a binary search is employed which reduces the compile time required to determine maximum load latency for which registers can be assigned.

Abstract: In some embodiments, a computer system comprises a cache configured to cache data. The computer system is configured to monitor the cache and data that is potentially cacheable in the cache to accumulate a plurality of statistics useable to identify which of a plurality of data lifecycle patterns apply to the data. The computer system is also configured to modify a cache configuration of the cache dependent on which of the plurality of data lifecycle patterns apply to the data.

Abstract: In one embodiment, a processor comprises a plurality of processor cores and an interconnect to which the plurality of processor cores are coupled. Each of the plurality of processor cores comprises at least one translation lookaside buffer (TLB). A first processor core is configured to broadcast a demap command on the interconnect responsive to executing a demap operation. The demap command identifies one or more translations to be invalidated in the TLBs, and remaining processor cores are configured to invalidate the translations in the respective TLBs. The remaining processor cores transmit a response to the first processor core, and the first processor core is configured to delay continued processing subsequent to the demap operation until the responses are received from each of the remaining processor cores.

Abstract: A method for tracing of instructions executed by a processor is provided which includes providing a type of instruction to be traced and tracing at least one instruction corresponding to the type of instruction. The method further includes storing data without stopping from the tracing into a memory until the memory is full.

Abstract: One embodiment of the present invention provides a system that asynchronously controls the sending of data items from a sender to a receiver. The system includes a data path between the sender and the receiver, a first control path between the sender and the receiver, and a second control path between the sender and the receiver. The first control path and the second control path alternately control the asynchronous transmission of consecutive data items on the data path between the sender and the receiver.

Abstract: A mapping engine, capable of receiving descriptions of manageable software objects in a first language, for generating management information in a second language. The mapping engine is further capable of generating a set of mapping metadata, corresponding to the management information as generated. The mapping engine may be further responsive to user input. In another embodiment, a metadata compiler is provided, capable of receiving management information in a second language, and corresponding mapping metadata, for generating compiled metadata, applicable when using said management information in a first language. The metadata compiler may be used in connection with the above first aspect.

Abstract: A method and apparatus for determining whether a TCP packet lands in-zone or out-of-zone of a TCP sequence space. An anchor representing the TCP sequence number of the last TCP data byte, plus one, is updated each time a TCP data packet is received. When a new TCP packet is received, the most significant bit, bit [31], is extracted from the anchor. A two-bit value is formed by adding 1 to the extracted bit. This two-bit value is pre-pended to bits [30:0] of the anchor, as bits [32:31], to produce a 33-bit test value. Then, the sequence number of the last TCP byte of the received packet is then compared to the anchor and the test value. If the sequence number is greater than or equal to the anchor, and less than the test value, the packet lands in-zone and may be processed normally.

Abstract: A system is provided for detecting when a temperature of a multiprocessor chip approaches an established threshold temperature indicating an imminent overheat condition. When the threshold temperature is reached, a number of active threads are idled in order to remove their contribution from the overall power consumption of the multiprocessor chip. Idling of the threads serves to prevent the multiprocessor chip from reaching the overheat condition. Once the temperature of the multiprocessor chip drops to an acceptable level, execution of the previously idled threads is resumed. Detection of the imminent overheat condition and corresponding idling of the threads to avoid reaching the overheat condition is conducted by hardware to ensure timely reduction of the multiprocessor chip temperature.

Abstract: A method for caching in a tracing framework, including firing a probe associated with a thread, evaluating a first predicate of the probe, caching the first predicate in a predicate cache associated with the thread, based on the evaluating of the first predicate and cacheability of the first predicate, and transferring control to the thread, based on the caching.

Abstract: A method for managing memory in a multi-tasking virtual machine, involving suspending a first task for garbage collection of a plurality of concurrently executing tasks, promoting at least one object associated with the first task to a old generation using a gap buffer to obtain a promoted object, wherein the gap buffer stores a gap created by objects directly allocated by at least one of the plurality of concurrently executing tasks, locating the promoted object using the gap buffer, traversing the promoted object to determine whether a first referenced object exist, and promoting the first referenced object using the gap buffer, if the first referenced object exists.

Abstract: An improved mechanism for tracking the execution progress of a task is disclosed. In one implementation, the execution progress of a parent task and one or more child tasks is monitored. The parent task spawns the one or more child tasks, and the child tasks execute concurrently with the parent task. In addition to monitoring the execution progress of the tasks, an overall execution progress value is determined for the parent task. In one implementation, the overall execution progress value is determined based, at least partially, upon the execution progress of the parent task and the execution progress of at least one of the child tasks. By taking the execution progress of the child tasks into account, the overall execution progress value reflects not just the progress made by the parent task itself but also the progress made by the child tasks that it spawned.

Abstract: A decoupling package stack including a circuit board, a substrate mounted on and electrically coupled to the circuit board, a semiconductor die mounted on and electrically coupled to the substrate a deformable elastomeric support mounted on the substrate, one or more mounts coupled to the circuit board and a heatsink. The heatsink includes a contoured heatsink base having a spacer attached thereto, the spacer operable to determine and maintain a desired bondline of a first thermal interface material (TIM) between the semiconductor die and the contoured heatsink base. The heatsink also includes one or more contact portions for contacting the deformable elastomeric support and one or more compressing surfaces coupled to the one or more mounts. A method for assembling a decoupling package stack.

Abstract: Deployment of an RFID system in a business entails a thorough analysis of the 3-dimensional topography in which it is deployed. A deployment field may have multiple floors, multiple entries, multiple exits, and multiple zones and fronts. A graphical deployment application, or visual design tool, provides a graphical representation of the deployment area. Such an application allows visual manipulation of the RFID components in the area to generate realtime graphical feedback about the operation of the dynamically configured deployment. The graphical user interface (GUI) based application receives parameters and variables defining the deployment area and the attributes of the transceivers and transponders for deployment therein. The application identifies a zone of readability of transponders in an area and visually displays such a zone along with the RFID components to determine placement of transceivers accordingly.

Abstract: Efficient development of conventional web applications suggests extensive and thorough knowledge of web page delivery technologies such as HTML, Java, and JSPs. A rendering framework to define the static, cosmetic, “window dressing” type of content, replicated across multiple pages, in a single JSP template file which can then incorporate or include the dynamic, active content from other files, mitigates development inefficiencies. Such a rendering framework represents each screen output page by a file including the active content, while avoiding replication of the static content. Such inclusions may be nested in a hierarchical manner to enumerate the static content in one file and allow a web application to include active content according to a hierarchical inheritance. Metadata components, such as XML files, include the active content according to a predetermined declarative syntax, thereby facilitating implementation, which the framework then interprets into a resulting output page such as a JSP page.

Abstract: A system and method for error detection in a data storage array includes one or more storage medium interconnected with a controller through a network. A data integrity engine in the controller applies a first error detection process to a data object to create one or more data blocks and associated parity codes. First and second error detection processes are applied to detect and repair errors in the data object.

Abstract: Systems and methods are described for providing queue pair numbers for a queue pair to more effectively track and manage the frequency of use and re-use of queue pair numbers on a queue pair context basis in an InfiniBand™ device. The present invention uses a counter for each queue pair context to set the changeable portion of the queue pair number. A reference count for each queue pair context is also used to track the quantity of queue pair numbers currently allocated to a queue pair context. The present invention sets, tracks and manages the values of the counter and the reference count for each queue pair context in conjunction with queue pair operations to provide a systematic queue pair numbering scheme. By tracking and/or setting values of the counter and reference count for a queue pair context, the present invention re-uses queue pair numbers efficiently and in a predictable and repeatable manner.

Abstract: A system that facilitates distinguishing between soft errors and the onset of hardware degradation in a computer system. During operation, the system receives notifications of correctable-error events from a plurality of memory components. The system then averages numbers of correctable-error events from the plurality of memory components to generate an average number of correctable-error events across the plurality of memory components. The system subtracts the number of correctable-error events for a given memory component in a given time interval from the average number of correctable-error events to generate a residual number of correctable-error events for the given memory component in the given time interval.

Abstract: A method for accuracy-aware analysis of a program involving obtaining source code for the program comprising a floating point variable, instrumenting the source code to associate an accuracy-aware tracking structure with the floating-point variable to obtain instrumented source code, compiling to instrumented source code to obtain instrumented compiled code, and executing the instrumented compiled code, wherein executing the instrumented compiled code comprises using the accuracy-aware tracking structure to track an operation on the floating-point variable.

Abstract: A method for providing verification for a simulation design, including obtaining the simulation design comprising a programming language interface system call, encoding a target of the programming language interface system call into the simulation design to obtain a first modified simulation design, modifying the programming language interface system call to reference the target in the first modified simulation design to obtain a second modified simulation design, and verifying the second modified simulation design using a simulation testbench.