Abstract: An execution unit adapted to perform at least a portion of the Data Encryption Standard. The execution unit includes a Left Half input; a Key input; and a Table input. The execution unit also includes a first group of transistors configured to receive the Table input, perform a table look-up, and output data. The execution unit further includes a first exclusive-or operator having two inputs and an output. The first exclusive-or operator is configured to receive the Left Half input and the Key input. The execution unit also includes a second exclusive-or operator having two inputs and an output. The second exclusive-or operator is configured to receive the data output by the first group of transistors and to receive the output of the first exclusive-or operator. The execution unit also includes a third exclusive-or operator having two inputs and an output. The third exclusive-or operator is configured to receive the Left Half input and the data output by the first group of transistors.

Abstract: A method for inter-process communication between a first process and a second process. The method includes receiving a request from the first process for processing a first process call in a first programming language by the second process, where the second process is configured to execute in a second programming language. The method further includes providing the second process with a procedure to emulate the processing of the first process call, where the procedure is defined in a data structure. Finally, the method includes converting the first process call into a second process call to the procedure using the data structure, executing the second process call using the procedure to obtain a result, and returning the result to the first process.

Abstract: A method for scaling a network system which includes providing at least one network interface and providing a flexible association between packets and a plurality of processing entities via the plurality of memory access channels. Each network interface including a plurality of memory access channels.

Abstract: A circuit and method are provided for detecting a phase difference between at least two periodic signals. The circuit and method disclosed herein provide pulsed output signals with wide output pulse widths well suited for use to drive a charge-pump in a phase-locked loop. The wide pulse widths of the output signals generated by the circuit and method allow the charge-pump to sink or source current with higher accuracy and therefore improve the operational characteristics of the phase-locked loop. Further, the circuit and method disclosed herein allow a phase-frequency detector and an associated charge-pump to operate at a higher operational frequency due to the wide pulse widths.

Abstract: One embodiment of the present invention provides a system that facilitates debugging an integrated circuit without probing signal lines within the integrated circuit. During operation the system updates a performance counter within the integrated circuit based on the occurrence of one or more performance events. Note that some integrated circuits already include a performance counter which is used to measure the performance of the integrated circuit. Next, the system triggers a debugging operation based on the content of the performance counter, thereby facilitating debugging of the integrated circuit without probing signal lines within the integrated circuit. By using the performance counter to trigger the debugging operation in addition to measuring performance, the present invention can substantially reduce the amount of additional circuitry required to facilitate debugging of the integrated circuit.

Abstract: A mechanism for securely decompiling representations of objects into copies of the objects is described. A virtual machine may include extensions for decompiling data representation language representations of objects into objects. The decompiler API may accept a data stream, which includes a representation of the object, and output a copy of the object. In one embodiment, during the decompilation of the representation of objects on a client, each message may be checked to verify that the user has access rights to the object. Access right information for the object may be embedded in the message(s) containing the representation of the object. In one embodiment, when the user is done using the client, the user may log off or otherwise signal the user is finished with the client. The client may detect that the user is finished, and may then proceed to delete objects created by decompilation of representations.

Abstract: An invention is provided for provisioning services to client devices. In one embodiment, discovery transactions are included that allow an adapter software component to retrieve information regarding services available to a client device from a provisioning application. A service comprises a plurality of content files capable of being installed on the client device. Also included are subscription transactions that allow an adapter software component to manage content in service directories. A service directory comprises a plurality of services. In addition, delivery transactions are included that allow an adapter to facilitate downloading of data related to services to the client device.

Abstract: A floating point flag combining or accumulating circuit includes an analysis circuit that receives a plurality of floating point operands, each having encoded status flag information, and a result assembler. The analysis circuit analyzes the plurality of floating point operands and provides an indication of one or more predetermined formats in which the plurality of floating point operands are represented. The result assembler receives the indication from the analysis circuit and assembles an accumulated result that represents a value and combines the encoded status flag information from at least two of the plurality of floating point operands.

Abstract: Embodiments of a request failover mechanism may be used to failover requests from clients of server instances in a cluster to alternative server instances. One embodiment may use cluster-aware remote references that include the IIOP endpoints at which the application server instances forming the cluster listen to IIOP requests. Using a cluster-aware remote reference to an object on an application server instance, a request to the object may be failed-over to an alternate endpoint in the cluster when the primary endpoint is unreachable. In one embodiment, once a request for a referenced object is failed over to a new server instance, all the subsequent requests to that object will continue to go to the same server instance even if the original server instance becomes available. One embodiment may provide client-side IIOP request load balancing in clustered application server environments through a load balancer subsystem using the cluster-aware remote references.

Abstract: One embodiment of the present invention provides a system that facilitates applying a dynamic lock to a range of a resource within a computer system. Upon receiving a request to lock to the range of the resource from a thread, the system examines an active lock pool to determine if the range of the resource is currently locked. If not, the system retrieves a dynamic lock from a free lock pool. Next, the system sets resource information in the dynamic lock so that the dynamic lock is associated with the resource. The system also sets owner information in the dynamic lock so that the dynamic lock is associated with the thread that is requesting the dynamic lock. Finally, the system adds the dynamic lock to the active lock pool.

Abstract: A method, computer program, and apparatus verify instructions in a module of a computer program during linking using pre-verification constraints with fully lazy loading. It is first determined whether a first module which is loaded has passed verification one-module-at-a-time before linking. If the first module has passed verification, a pre-verification constraint on a constrained module is read, if any. It is then determined if the constrained module is loaded, if any pre-verification constraint is read. If the constrained module is not already loaded, the pre-verification constraint is retained as a verification constraint.

Abstract: A reduced-power memory (such as for a cache memory system of a processor or a microprocessor) provides per-sector ground control to advantageously reduce power consumption. Selective power control of a plurality of sectors comprised in the reduced-power memory is responsive to a subset of address bits for accessing the memory. The selective power control individually powers-up a selected one of the sectors in response to an access, and then powers-down the selected sector when the access is complete. The power-up is via a decrease in ground potential from a retention level to an access level. Time needed to vary the ground potential is optionally masked by providing address information used by the selective power control in advance of providing other address information. For example, in a cache, a tag access is overlapped with power-up of a selected sector, thus masking latency of powering up the selected sector.

Abstract: One embodiment of the present invention provides a system for routing data between integrated circuit devices. This system couples together an n-dimensional grid of integrated circuit devices using multiple independent communication networks, wherein each of the communication networks only moves data in two orthogonal directions (e.g., North and East, North and West, South and East, or South and West). The system also includes a routing mechanism that routes data across these communication networks, as well as, into, out of, and through integrated circuits within the n-dimensional grid of integrated circuits. Note that the process of routing a signal across a given network is greatly simplified because it is not possible to create a cycle that causes a deadlock within a given network.

Abstract: First and second host systems can each include a respective repository of host identities. The first host system can encode a host identity to be transferred to the second host system using a parameter, for example a property of the second host system. The first host system can divulge the result of the encoding and remove the host identity from its repository. The second host system can decode the host identity to be transferred using the parameter, and can then add the host identity to be transferred to its repository.

Abstract: A method and system for trace generation using memory index hashing. A method may include generating an extended trace representative of M threads of instruction execution from a trace representative of N threads of instruction execution, where N and M are integers, N?1 and M>N, and where each of the N threads of the trace includes memory references to respective memory addresses. Generating the extended trace from the trace may include replicating the N threads to generate the M threads, assigning a respective identifier to each of the M threads, and for a given one of the M threads, hashing a first portion of each of the respective addresses dependent upon the respective identifier of the given thread, where the first portion of each of the respective addresses corresponds to at least part of an index of a memory structure shared by at least two of the M threads.

Abstract: A system links architecture neutral code downloaded to a resource constrained computer. The code may be separated into one or more packages having one or more referenceable items. The system maps the one or more referenceable items into corresponding one or more tokens; orders the tokens to correspond to a run-time mode; downloads the packages to the resource constrained computer; and links the packages into an executable code using the ordered tokens.

Abstract: A method is disclosed for obtaining data from a kernel, including obtaining data from the kernel, and storing the data in a data set an aggregation buffer using an aggregation function. A method is disclosed for storing data in a data set, wherein the data set includes a key component, an aggregation identifier component, and a value component, including obtaining an expression, a new value, and an aggregation identifier, generating a key using the expression and the aggregation identifier; and storing the data set in a buffer, wherein storing the data set comprises storing the key in the key component, storing the aggregation identifier in the aggregation identifier component, and updating a current value in the value component using the new value and an aggregation function.

Abstract: A method, system and computer program product that involves receiving and initializing a digital image. Quantization is preformed on the digital image using at least two multiplication operations. Finally, a compressed version of the digital image is presented for viewing and/or storage or transport.

Abstract: A stable power, low electromagnetic interference (EMI) apparatus and method for connecting electronic devices and circuit boards is disclosed. The apparatus involves a capacitor which includes a body member, a set of power terminals and a set of ground terminals connected to the top of the body member. The set of power terminals and the set of ground terminals alternate one with another. As a result of this configuration, a high inductance on the PCB side is achieved. The capacitor further includes a set of terminals connected to the bottom of the body member and includes metal planes within the body member. The metal planes are positioned to electrically connect either the set of power terminals or the set of ground terminals to the set of terminals.

Abstract: A blade server includes a chassis; a first plurality of bays in the chassis, wherein the first plurality of bays is adapted to receive and at least partially house a plurality of CPU modules, and wherein the first plurality of bays is accessible through a first side of the chassis; a second plurality of bays in the chassis, wherein the second plurality of bays is adapted to receive and at least partially house a plurality of PCI-Express modules, and wherein the second plurality of bays is accessible through a second side of the chassis; and a midplane board arranged to pass a PCI-Express signal between at least one of the plurality of CPU modules and at least one of the plurality of PCI-Express modules.