Patents Assigned to Sun Microsystems
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Patent number: 7437505Abstract: A computer readable medium includes executable instructions for visually representing a status of a plurality of storage device slots and a plurality of attached storage devices by, and a method for visually representing a status of a plurality of storage device slots and a plurality of attached storage devices includes, assigning a logical name to a storage device slot based on an enumeration rule; detecting a storage device attached to a computer system; storing a correlation between a physical location of the storage device slot and the assigned logical name; monitoring an availability and an operating status of the plurality of storage device slots and the plurality of attached storage devices; and generating a what-you-see-is-what-you-get (WYSIWYG) representation of the plurality of storage device slots and the plurality of attached storage devices, wherein the WYSIWYG representation includes physical location information, operating status information, and logical names for the plurality of storage devicType: GrantFiled: May 24, 2006Date of Patent: October 14, 2008Assignee: Sun Microsystems, Inc.Inventor: Michael N. Chew
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Patent number: 7437716Abstract: A method for storing a data set having an enabled probe identification component and an associated data component, including obtaining data from an instrumented program using a probe, associating the data with an enabled probe identification, and storing the data in the data set, wherein the enabled probe identification is stored in the enabled probe identification component and the data is stored in the associated data set component.Type: GrantFiled: November 14, 2003Date of Patent: October 14, 2008Assignee: Sun Microsystems, Inc.Inventor: Bryan M. Cantrill
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Patent number: 7437612Abstract: In general, in one aspect, the invention relates to a method for identifying lock ownership, including identifying at least one node in the crash dump, characterizing the at least one node in the crash dump as a node of inferred type and appending the at least one node to a list of nodes of inferred type, determining whether each node in the list of nodes of inferred type is a structure, and for each node in the list of nodes determined to be a structure determining whether each member in each node corresponds to a lock, and determining an owner of the lock.Type: GrantFiled: September 21, 2004Date of Patent: October 14, 2008Assignee: Sun Microsystems, Inc.Inventor: Bryan M. Cantrill
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Publication number: 20080250088Abstract: The invention relates to a method for performing generational garbage collection on a heap comprising a plurality of generations. The method involves dividing a young generation of the heap into a first young generation and a second young generation, evacuating the first young generation concurrently with allocating the second young generation, and evacuating the second young generation concurrently with allocating the first young generation and subsequent to fully evacuating the first young generation.Type: ApplicationFiled: April 3, 2007Publication date: October 9, 2008Applicant: Sun Microsystems, Inc.Inventors: Antonios Printezis, Alexander T. Garthwaite
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Patent number: 7433912Abstract: A unified data flow is provided that allows multiplication of SIMD and non-SIMD multiplies in one multiplier. The multiplies may be both integer and floating point operations. The multiplier is partitionable having a plurality of sub-trees. The multiplier is configured to be a single tree structure in response to a non-SIMD multiplication instruction and as a partitioned tree structure in response to a SIMD multiplication instruction. At least two multiplication operations can be performed in parallel in the partitioned tree structure in response to the SIMD multiplication instruction and a single multiplication operation is performed in the single tree structure in response to the non-SIMD multiplication instruction. Appropriate formatting of the input operands and selection of data from the tree structures is performed in accordance with the instruction.Type: GrantFiled: February 19, 2004Date of Patent: October 7, 2008Assignee: Sun Microsystems, Inc.Inventors: Paul J. Jagodik, Jeffrey S. Brooks, Christopher Olson
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Patent number: 7434210Abstract: A method for checking page size dependency including generating an interposing library comprising a first modified interface, wherein the first modified interface is dependent on a native page size, intercepting a call into a kernel by the interposing library, wherein the call is dependent on a non-native page size, modifying the call using the first modified interface to obtain a modified call, and generating a response to the modified call by the kernel using the native page size.Type: GrantFiled: March 2, 2004Date of Patent: October 7, 2008Assignee: Sun Microsystems, Inc.Inventor: Andrew G. Tucker
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Patent number: 7434087Abstract: Various embodiments of a system and method for failing over one cluster node to another are disclosed. The system may include a client networked to a cluster of computer nodes, connected to a persistent data store such as a database resident on a backend system. Each node of the cluster may be configured to run a distributed application component. The client may be configured to communicate with an instance of the application running on a first node. The client may include an augmented stub capable of accessing the instance of the application on the first node and capable of detecting a failure of the first node. In response to detecting a failure in the first node, the augmented stub may be capable of failing over to a second node and accessing the instance of the application on the second node, transparently to the client.Type: GrantFiled: May 21, 2004Date of Patent: October 7, 2008Assignee: Sun Microsystems, Inc.Inventor: Servesh Pratap Singh
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Patent number: 7434213Abstract: Platform independent processing of the source code is performed, such as lexical analysis, semantic analysis, syntax analysis, and platform independent optimization, and an intermediate representation of the source code is generated. This intermediate representation is carried forward into the next stage of processing, which is platform dependent processing. The intermediate representation undergoes machine specific analysis and an executable representation (i.e., executable code) of the source code for a particular platform is generated. However, the intermediate representation, which has not been converted to a machine specific representation, is included with the executable representation. The source code can essentially be ported to a different platform by extracting the intermediate representation and performing platform dependent processing on the intermediate representation.Type: GrantFiled: March 31, 2004Date of Patent: October 7, 2008Assignee: Sun Microsystems, Inc.Inventors: Raj Prakash, Kurt J. Goebel, Fu-Hwa Wang
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Patent number: 7434156Abstract: Provided is a method, system, program, and computer readable medium for maintaining a database of objects. At least one structured document is received representing an instance of an object including attributes and attribute values defined for a class. Content of the structured document representing the object is added into the database, wherein the database is capable of storing multiple structured documents representing multiple objects. In another implementation, an instance of at least one object including attributes and attribute values defined for a class is generated. For each generated object, a structured document is generated representing the object and including a representation of the attributes and attribute values in the object. Each structured document is transferred to the database to maintain.Type: GrantFiled: November 27, 2000Date of Patent: October 7, 2008Assignee: Sun Microsystems, Inc.Inventors: Terence Leong, Mahima Mallikarjuna, Julian Taylor
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Patent number: 7434031Abstract: RAW aliasing can be predicted with register bypassing based at least in part on execution displacement alias prediction. Repeated aliasing between read and write operations (e.g., within a loop), can be reliably predicted based on displacement between the aliasing operations. Performing register bypassing for predicted to alias operations facilitates faster RAW bypassing and mitigates the performance impact of aliasing read operations. The repeated aliasing between operations is tracked along with register information of the aliasing write operations. After exceeding a confidence threshold, an instance of a read operation is predicted to alias with an instance of a write operation in accordance with the previously observed repeated aliasing. Based on displacement between the instances of the operations, the register information of the write operation instance is used to bypass data to the read operation instance.Type: GrantFiled: April 12, 2004Date of Patent: October 7, 2008Assignee: Sun Microsystems, Inc.Inventors: Lawrence A. Spracklen, Santosh G. Abraham, Stevan Vlaovic
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Patent number: 7434051Abstract: One embodiment of the present invention provides a system that facilitates confirmation of data communicated to a first device belonging to a first user from a second device belonging to a second user. During operation, the first device receives a message containing data from the second device. The first device then translates the data into a string of words (such as a human-friendly representation using a well-known function such as the One Time Password (OTP) dictionary defined in IETF RFC 1938) that can be recognized by a human. Next, the first device displays the string of words to the first user. The second device also translates the original data using the same well-known function. The first user and the second user then confirm that both strings of words match. The confirmation process is performed through a separate communication channel. This confirmation process ensures that the data sent by the second device is successfully received by the first device, and that it was sent by the second device.Type: GrantFiled: September 29, 2003Date of Patent: October 7, 2008Assignee: Sun Microsystems, Inc.Inventors: Gabriel Montenegro, Damine Bailly
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Patent number: 7434000Abstract: In one embodiment, a processor comprises a cache and a cache miss unit coupled to the cache. The cache miss unit is configured to initiate a cache fill of a cache line for the cache responsive to a first cache miss in the cache, wherein the first cache miss corresponds to a first thread of a plurality of threads in execution by the processor. Furthermore, the cache miss unit is configured to record an additional cache miss corresponding to a second thread of the plurality of threads, wherein the additional cache miss occurs in the cache prior to the cache fill completing for the cache line. The cache miss unit is configured to inhibit initiating an additional cache fill responsive to the additional cache miss.Type: GrantFiled: December 9, 2004Date of Patent: October 7, 2008Assignee: Sun Microsystems, Inc.Inventors: Jama I. Barreh, Manish K. Shah
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Patent number: 7434004Abstract: Predicting prefetch data sources for runahead execution triggering read operations eliminates the latency penalties of missing read operations that typically are not addressed by runahead execution mechanisms. Read operations that most likely trigger runahead execution are identified. The code unit that includes those triggering read operations is modified so that the code unit branches to a prefetch predictor. The prefetch predictor observes sequence patterns of data sources of triggering read operations and develops prefetch predictions based on the observed data source sequence patterns. After a prefetch prediction gains reliability, the prefetch predictor supplies a predicted data source to a prefetcher coincident with triggering of runahead execution.Type: GrantFiled: June 17, 2004Date of Patent: October 7, 2008Assignee: Sun Microsystems, Inc.Inventors: Lawrence A. Spracklen, Santosh G. Abraham, Stevan Vlaovic, Darryl J. Gove
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Patent number: 7433396Abstract: Disclosed are novel methods and apparatus for efficiently providing equalization in single-ended chip-to-chip communication. In an embodiment, a method of adjusting signal levels to provide improved communication between a sender device and a receiver device is disclosed. The method includes providing a plurality of voltage dividers. The plurality of voltage dividers may be coupled to each other to provide a reference voltage to the receiver device. The method further includes providing a storage device to store previously received data by the receiver device and providing a controller to selectively activate the plurality of voltage dividers.Type: GrantFiled: March 28, 2002Date of Patent: October 7, 2008Assignee: Sun Microsystems, Inc.Inventor: Aninda Roy
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Publication number: 20080238474Abstract: A booster circuit for reducing the nominal latency of a logic gate. The booster circuit includes a charge sharing mechanism to transfer a stored charge to the output of the logic gate in response to a logic state transition on the input of the logic gate. The transfer of stored charge also reduces the charge drawn from the supply during the output transition.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Applicant: Sun Microsystems, Inc.Inventor: Scott M. Fairbanks
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Publication number: 20080244185Abstract: The invention relates to a method for reducing cache flush time of a cache in a computer system. The method includes populating at least one of a plurality of directory entries of a dirty line directory based on modification of the cache to form at least one populated directory entry, and de-populating a pre-determined number of the plurality of directory entries according to a dirty line limiter protocol causing a write-back from the cache to a main memory, where the dirty line limiter protocol is based on a number of the at least one populated directory entry exceeding a pre-defined limit.Type: ApplicationFiled: March 28, 2007Publication date: October 2, 2008Applicant: Sun Microsystems, Inc.Inventors: Brian W. O'Krafka, Roy S. Moore, Pranay Koka
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Publication number: 20080244613Abstract: A method for processing a message that includes receiving the message by a plurality of resource adapters (RA), wherein each RA corresponds to a different application instance of a plurality of application instances, calculating, by each RA of the plurality of RAs, a selector string using an application instance selection portion of the message, determining, by each RA of the plurality of RAs, whether the selector string calculated by the RA identifies the application instance corresponding to the RA, transmitting the message, by each RA of the plurality of RAs, to the application instance corresponding to the RA when the selector string calculated by the RA identifies the application instance, and discarding the message, by each RA of the plurality of RAs, when the selector string calculated by the RA does not identify the application instance corresponding to the RA, wherein one RA of the plurality of RAs transmits the message to the application instance corresponding to the RA and the remaining RAs of theType: ApplicationFiled: March 27, 2007Publication date: October 2, 2008Applicant: Sun Microsystems, Inc.Inventors: Ramesh Parthasarathy, Binod P. Gangadharan, Sivakumar Thyagarajan
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Publication number: 20080238616Abstract: The present invention relates to a method for message delivery from a sender process to a receiver process within a computer system, comprising performing an atomic check for the receiver process and a parent of the receiver process, returning a first status of the receiver process and a second status of the parent of the receiver process based on the atomic check, and delivering the message according to the first status and the second status, wherein the first status and the second status stay unchanged during the atomic check.Type: ApplicationFiled: March 28, 2007Publication date: October 2, 2008Applicant: Sun Microsystems, Inc.Inventors: Chrislain Razafimahefa, Krzysztof Palacz, Grzegorz Jan Czajkowski, Laurent Philippe Daynes
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Publication number: 20080240142Abstract: A method for obtaining a capability from a network interface card (NIC), involving sending a query to the NIC for the capability, obtaining the capability from the NIC in response to the query, sending the capability to a virtual NIC, and sending the capability from the virtual NIC to a virtual network stack associated with the virtual NIC, wherein the capability is used by the virtual network stack to process packets.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Applicant: Sun Microsystems, Inc.Inventors: Kais Belgaied, Darrin P. Johnson
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Publication number: 20080244016Abstract: A method for processing a message by a message provider that includes receiving, for a topic, a mutual exclusion function from each application instance of a plurality of application instances, receiving the message for the topic, and sending the message to one application instance of the plurality of application instances based on executing each of the mutual exclusion functions, wherein the mutual exclusion functions ensure that the message is sent to a single application instance of the plurality of application instances.Type: ApplicationFiled: March 27, 2007Publication date: October 2, 2008Applicant: Sun Microsystems, Inc.Inventors: Ramesh Parthasarathy, Binod P. Gangadharan, Sivakumar Thyagarajan