Abstract: A method for data analysis of power modeling for a microprocessor has been developed. The method takes multiple values of power data from a power modeling simulator and generates summary data to characterize the power data behavior. Summary data views include results characterizing behavior in a single cycle and behavior across multiple cycles. Data is viewed both at an absolute level to characterize total power and relative to previous levels to characterize power derivatives. Summary data is derived from power generated every cycle when running specific benchmark programs on the power simulator.

Abstract: A method for concurrent garbage collection and mutator execution in a computer system includes scanning a first cache line for a non-local bit. The non-local bit is associated with a root object. A done bit associated with the first cache line is set. A second cache line to find a first object that is referenced by the root object is located. A mark bit and the done bit associated with the second cache line are set. The first and second cache lines are scanned for unset done bits. If an unset done bit is detected in either the first or the second cache line, then the cache line associated with the unset done bit is rescanned to determine whether there are any modified object references.

Abstract: A Java virtual machine includes a just in time (JIT) Java compiler. The JIT compiler includes at least one optimizer. Each of the at least one optimizer includes logic for recognizing a pattern in a received Java byte code, logic for optimizing the recognized pattern to produce optimized native code and logic for outputting optimized native code. A method of producing optimized native code is also provided.

Abstract: In one embodiment of the present invention, a voice control application transmits data to a voice server about a first execution state of an application program resident in the memory of an electronic device having a first graphical display. The voice control application also transmits an audio waveform encoding of a voice command defining a second execution state of the application program. The voice server performs a speech recognition process upon the audio waveform encoding and transmits a reply to the electronic device for causing the second execution state of the application program. The voice control program, in response to the response, automatically causes the second execution state of the application program having a second graphical display.

Abstract: A system and method for dynamically and persistently tracking incremental profiling data in a process cloning application environment is presented. A master runtime system process is executed. A memory space of the master runtime system process is cloned as a child runtime system process responsive to a process request. The child runtime system process is executed. The execution of the child runtime system process is profiled by collecting profiling data incrementally. The child runtime system process profiles are fed back to the master runtime system process to benefit subsequent cloned child runtime system processes. In a further embodiment, the child runtime system process profiles are maintained in a persistent storage for use by the master runtime system process upon the next start up.

Abstract: One embodiment of the present invention provides a system that facilitates concurrent non-transactional operations in a transactional memory system. During operation, the system receives a load instruction related to a local transaction. Next, the system determines if an entry for the memory location requested by the load instruction already exists in the transaction buffer. If not, the system allocates an entry for the memory location in the transaction buffer, reads data for the load instruction from the cache, and stores the data in the transaction buffer. Finally, the system returns the data to the processor to complete the load instruction. In this way, if a remote non-transactional store instruction is received during the transaction, the remote non-transactional store proceeds and does not cause the local transaction to abort.

Abstract: A value that bypasses some of the computations for an arithmetic operation can be supplied for performance of a dependent arithmetic operation without waiting for completion of the computations of the arithmetic operation. During performance of a first arithmetic operation, a value is generated. The value is viable for use in performing a second arithmetic operation that is dependent upon the first arithmetic operation. The value is utilized to continue performance of the first arithmetic operation and commence performance of the second arithmetic operation. As part of the continued performance of the first arithmetic operation, determining whether the value is to be modified for the first arithmetic operation. Compensating for modifications to the value for performance of the second arithmetic operation.

Abstract: A method of analyzing a circuit simulation comprising pruning a signal flow graph. Pruning the signal flow graph includes selecting a current vertex from a multiple input vertices in the signal flow graph. Each one of the input vertices is connected to a primary input of the signal flow graph. Determining if the current vertex includes at least one of a sensitivity parameter or a sensitivity variable. If the current vertex includes at least one of a sensitivity parameter or a sensitivity variable then the current vertex is identified as being part of a sensitivity path and is added to a first sub-group of vertices. Pruning the signal flow graph also includes determining if any remaining non-visited neighbor vertices remain to be analyzed. If any remaining non-visited neighbor vertices remain to be analyzed then selecting a neighboring vertex and determining if the selected neighbor vertex is identified as a sensitivity path.

Abstract: Embodiments of the present invention provide a system that electronically aligns mini-bars on different semiconductor chips which are situated face-to-face to facilitate communication between the semiconductor chips through capacitive coupling. During operation, the system selects a group of transmitter mini-bars on the first chip to form a transmitter bit position and selects a group of receiver mini-bars on the second chip to form a receiver bit position. The system then associates transmitter bit positions on the first chip with proximate receiver bit positions on the second chip. In this way, the system allows data signals transmitted by the mini-bars within a transmitter bit position on the first chip to be collectively received by the mini-bars within an associated receiver bit position on the second chip.

Abstract: A single-chip module is described. The module includes a first semiconductor die having a first surface and a second surface. The first semiconductor die is configured to communicate by capacitive coupling using one or more of a plurality of proximity connectors coupled to the first semiconductor die. A cable coupled to the first semiconductor die is configured to couple power signals to the first semiconductor die. A flexibility compliance of at least one section of the cable is greater than a threshold value thereby allowing the module to be positioned in a mounting structure.

Abstract: One embodiment of the present invention provides a system that supports executing a fail instruction, which terminates transactional execution of a block of instructions. During operation, the system facilitates transactional execution of a block of instructions within a program, wherein changes made during the transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes. If a fail instruction is encountered during this transactional execution, the system terminates the transactional execution without committing results of the transactional execution to the architectural state of the processor.

Abstract: One embodiment of the present invention provides a system for high-throughput asynchronous communication that includes a sender and a receiver. A sender's first-in, first-out (FIFO) buffer is coupled to an input of the sender, a receiver's FIFO buffer is coupled to an input of the receiver, a forward communication channel is coupled between the sender and the receiver's FIFO buffer, and a reverse communication channel is coupled between the receiver and the sender's FIFO buffer. The forward communication channel, the receiver's FIFO buffer, the reverse communication channel, and the sender's FIFO buffer operate collectively as a network FIFO between the sender and the receiver. The network FIFO is configured to ensure that asynchronous communication between the sender and the receiver takes place reliably and without unnecessary waiting by the sender or the receiver.

Abstract: A method for optimizing a register file hierarchy in a multithreaded processor. The method includes providing a register file hierarchy with a plurality of register file cells, associating the plurality of register file cells with respective threads when the processor is operating in a multithreaded mode and flattening the plurality of register file cells with a single thread when the processor is operating in a single threaded mode. The register file cells correspond to threads of the multithreaded processor.

Abstract: A network address assignment server is disclosed, which is capable of dynamically updating its own configuration information during runtime. The configuration information (which may include, for example, one or more network addresses that can be assigned by the server, an association between a device identifier and a specific network address, etc.) may be updated and then used by the server without restarting the server. As a result, the server can update its configuration information without incurring any server downtime.

Abstract: A cooling apparatus uses a plurality of pipes to cool one or more integrated circuits disposed on a circuit board. The cooling apparatus uses an array of magnets to create magnetic fields across segments of the plurality of pipes. Electrical currents are induced across the magnetic fields. A flow of electrically conductive fluid in the plurality of pipes is dependent on and controllable by the magnetic fields and/or the electrical currents.

Abstract: A method for safepointing a system that includes receiving a stop command by an executing thread from a master, wherein the executing thread executes an operating system, continuing execution of the executing thread until a safepoint is reached after receiving the stop command, halting execution of the executing thread at the safepoint; and evaluating a response from the executing thread to diagnosis the system.

Abstract: A mechanism is disclosed for allowing an application to perform specified operations in response to occurrences of a specified event relative to a specified Smart Card-accessing device. A customized API is exposed to the application. The application invokes an “addEventListener” method of the API. The invocation of the method specifies, as parameters of the method, at least a Smart Card-accessing device, a type of event, and a function. The server computer executing the application detects the invocation of the “addEventListener” method. In response to detecting the invocation, the server determines the type of the event specified by the invocation, and starts a mechanism that executes the specified function each time that an event of the specified type occurs relative to the specified Smart Card-accessing device. Consequently, the application does not need to be programmed to poll the specified Smart Card-accessing device at specific times during the application's execution.

Abstract: One embodiment of the present invention provides a system that samples instructions on a processor that supports speculative-execution. The system starts by selecting an instruction, wherein selecting an instruction involves selecting an instruction that is received from an instruction fetch unit or a deferred queue, wherein the deferred queue holds deferred instructions which are deferred because of an unresolved data dependency. The system then records information about the selected instruction during execution of the selected instruction, whereby the recorded information can be used to determine the performance of the processor.

Abstract: A mechanism for managing network devices using a server with multiple network interfaces includes management agents executing on managed devices, wherein all the agents that share a single instance of a management server, or that are logically partitioned, are said to be in a single “server context”. Each server context can manage devices from any of multiple network interfaces of a server machine, that are associated with a given server context. Managed devices that are registered to be managed as part of a given server context are managed based on policies associated with the server context. Managed devices that are registered to be managed through one network interface of a server context of the management server may be communicatively isolated from managed devices that are registered to be managed through another network interface of the same server context of the management server.

Abstract: A hardware implemented method for resolving collisions of memory addresses of a memory array is provided. In this hardware implemented method, a read memory address is compared with a write memory address. If the read and write memory addresses match, write data is directed from a data input to a data output, whereby the data input is further configured to input the write data to the memory array. A system and a memory chip for resolving collisions of memory addresses of a memory array are also described.