Abstract: A method of operating a network system may involve receiving data indicating a configuration of components that are included in the network system, detecting a failure of one of the components, computing an availability (e.g., by calculating the instantaneous availability) of the network system from the data in response to detecting the failure, and storing data indicative of the availability of the network system.

Abstract: A system and method for dynamic preloading of classes through memory space cloning of a master runtime system process is presented. A master runtime system process is executed. A representation of at least one class is obtained from a source definition provided as object-oriented program code. The representation is interpreted and instantiated as a class definition in a memory space of the master runtime system process. The memory space is cloned as a child runtime system process responsive to a process request and the child runtime system process is executed, inheriting the memory state of the parent, which reflects the data structures and state corresponding to the preloaded classes.

Abstract: A virtual machine (e.g. the Java Virtual Machine (JVM)) may include extensions for compiling objects (e.g. Java Objects) into data representation language (e.g. XML) representations of the objects, and for decompiling representations of objects into objects. The virtual machine may supply an API to the compilation/decompilation extensions. The compiler/decompiler API may accept an object as input, and output a data representation language representation of the object and all its referenced objects (the object graph) in a data stream. In addition, the compiler/decompiler API may accept a data stream, which includes a representation of the object and all its referenced objects (the object graph), and output the object (and all the objects in its object graph). In one embodiment, an intermediary format may be used to represent a data representation language document and may be dynamically processed to generate a class instance from the data representation language document.

Abstract: A buffer architecture enables linked lists to be used to administer virtual output queue buffering. The buffer has three random access memories (RAMs). A data RAM holds data. A free RAM holds a linked list of entries defining free space in the data RAM. Destination RAM holds a linked list of entries defining data in the data RAM to be forwarded to a destination.

Abstract: In one embodiment, a processor comprises a register file, register management logic coupled to the register file, and at least two sources of window swap operations coupled to the register management logic. The register management logic is configured to control an interface to the register file to switch register windows in the register file in response to one or more window swap operations. The sources of window swap operations and the register management logic are configured to cooperate according to an arbitration scheme to arbitrate between conflicting window swap operations to be performed using the interface. In one particular implementation, for example, block signals may be used from higher priority sources to lower priority sources to block issuance of window swap operations by the lower priority sources.

Abstract: A processing system is provided. The processing system includes a master system and a processing resource. The master system is designed to execute a service component and a system controller component. The processing resource is designed to register with the service component for a specific period of time. By registering with the look up service of the service component, the processing resource advertises the eligibility of the processing resource to execute a software processing job having a set of requirements. The system controller component is designed to search the look up service of the service component to locate the processing resource having a set of attributes that substantially matches the set of requirements of the software processing job.

Abstract: An interconnect apparatus includes a transaction packet buffer and control logic. The control logic can be operable sequentially to write transaction packets for transmission to the transaction packet buffer and to transmit the buffered transaction packets in sequence to a destination. The control logic can further be operable on receipt of a control packet indicative of non-receipt by the destination of a transmitted transaction packet to retransmit the non-received transaction packet and transaction packets transmitted from the transaction packet buffer subsequent to the non-received transaction packet.

Abstract: Executing an obfuscated application program comprises receiving an application program comprising application program instructions and application program data, determining an application program instruction location permutation to apply to a current instruction counter value, determining an application program data location permutation to apply to a current data location counter value, receiving the current instruction counter value, and applying the application program instruction location permutation to the current instruction counter value to obtain a reference to an application program instruction in an instruction stream to execute. If the application program instruction references application program data, the application program data location permutation is applied to data referenced by the application program instruction to obtain a reference to data to access. The data to access is interleaved with application program instructions in the instruction stream.

Abstract: System and method for bridging between inter-object communication interfaces, such as RMI and IIOP, may include in one embodiment a bridge mechanism that maintains a cache of reference objects. The key used for hashing in the cache may be based on the object identifier (OID) of the reference objects. In one embodiment, the integer value of the OID is generated and then converted to a string for use in caching the object. In one embodiment, objects are not marked for deletion from the cache until a client calls a remove method. In one embodiment, object references in the cache include a reference to an exported object. In one embodiment, unexport of the exported object is performed by a post-invoke mechanism of the bridge mechanism after the remove method has completed.

Abstract: A computer system, for example for use as a server, comprises a host processor, a service processor for providing system management functions within the computer system, and a user interface for receiving external commands and data for the service processor and/or the host processor, and for sending data from the service processor and/or the host processor. A device is provided for routing the commands and data to and from the user interface via the service processor only when the device receives a signal from the service processor. In the absence of the signal, the commands and data are sent between the user interface and the console interface bypassing the service processor. By this means, the host processor may be addressed even if the service processor malfunctions.

Abstract: One embodiment of the present invention provides a method and a system for tracking memory usage of tasks in a shared heap. The system performs a full garbage-collection operation on the shared heap, during which a base memory usage is determined for each task. The system then periodically samples task state during execution to generate an estimate of newly allocated memory for each task. The base memory usage and the estimate of newly allocated memory for each task are combined to produce an estimate of current memory usage for each task. This estimate of current memory usage is used to determine whether a task is likely to be violating a memory quota. If so, the system triggers a remedial action, which can include: a full garbage-collection operation; a generational garbage-collection operation; or generation of a signal which indicates that a memory quota violation has occurred.

Abstract: A method for providing verification for a first simulation image involves removing nodes from the first simulation image to produce an optimized image and an optimized nodes image, simulating the optimized image, invoking the optimized nodes image if debugging is selected, reconstructing a second simulation image using the optimized image and the optimized nodes image, simulating the second simulation image to gather simulation data, and debugging the first simulation image using simulation data.

Abstract: An interconnect apparatus provides for the buffering of information in respective transaction buffers according to transaction type. An additional buffer is dynamically assignable to one of the transaction buffers where additional capacity is required by that transaction buffer.

Abstract: A heat sink uses a pump assembly to generate a magnetic field. A direction of electrically and thermally conductive liquid flowing through the pump assembly is dependent on an orientation of the magnetic field and the direction of electrical current induced across flowing fluid in the magnetic field. In such a manner, cool liquid may be directed toward a heat source and warmer liquid may be directed to flow away from the heat source, where heat transfer occurs between the liquid and the heat sink. Additional pump assemblies that generate separate magnetic fields may be used to increase fluid flow volume, thereby increasing heat transfer away from the heat source.

Abstract: A set of structures and techniques are described herein whereby an exemplary concurrent shared object, namely a shared skip list, can be implemented in a lock-free manner. Indeed, we have developed a number of interesting variants of a lock-free shared skip-list, including variants that may be employed to provide a lock-free shared dictionary. In some variants, a key-value dictionary is implemented.

Abstract: A system for interfacing hardware emulation to software simulation environments may include a simulation node configured to simulate a first portion of a system under test and a hardware emulation node configured to emulate a second portion of the system under test. The hardware emulation node may also be configured to exchange simulation information (such as representations of signal values obtained as output from the emulated portion of the system under test) with the simulation node. The hardware emulation node may contain a field programmable gate array devices (FPGA) configured to perform the hardware emulation. The FPGA may be mounted on an expansion board, such as a PCI (Peripheral Component Interconnect) board.

Abstract: An interconnect apparatus provides for the buffering of information among a plurality of retry buffers in an output port. An additional buffer is dynamically assignable to one of the N retry buffer means where additional capacity is required by that retry buffer.

Abstract: A method for dynamic striping, involving receiving a request to write a data block into a storage pool, determining a physical disk location in the storage pool to store the data block using a dynamic striping policy, storing the data block at the physical disk location, and storing a first indirect block in the storage pool, wherein the first indirect block comprises the data block location and the data block checksum.

Abstract: A rackmount storage server has a printed circuit board (PCB) having connectors for connecting with a plurality of top-loading storage devices. A controller assembly having a PCI expansion slot, is arranged to operatively connect to the passive backplane from a rear side of the PCB. Further, the rackmount storage server has redundant cooling unit for facilitating air flow in an interior region of the rackmount storage server. Further, the rackmount storage server may have an integrated battery for saving power for use in case of, for example, a power failure.

Abstract: A system and method for inducing asynchronous behavioral changes in a managed application process is presented. An application manager process is executed. A managed application process is executed. At least one application provided as object-oriented program code under the control of a managed code platform is executed. The managed application process logically communicates with the application manager process. One or more constructors corresponding to notifiable objects provided as object-oriented program code are identified. Each constructor keeps track of instantiated notifiable objects in a list in the managed application process. A change request is broadcast to the managed application process. The notifiable objects tracked by each identified constructor are iterated over to effect a behavioral change in the managed application process.