Abstract: A duty cycle bounding circuit for restoring the unbounded duty cycle of a periodic signal such as a forwarded clock signal. The duty cycle bounding circuit comprises a state holding logic element, such as a C-element, and a delay line. The delay line feeds back an inverted version of the output of the state holding logic element to an input of the state holding logic element. The periodic signal is applied to another input of the state holding logic element.

Abstract: A method for implementing a security protocol, involving receiving a packet from a network connection, obtaining an identifier for one of a plurality of security association database (SADB) partitions associated with the packet, wherein each of the plurality of SADB partitions is associated with one of a plurality of packet destinations, applying a security association from the one of the plurality of SADB partitions to the packet, and sending the packet to the one of the plurality of packet destinations associated with the SADB partition, wherein the packet is processed at the one of the plurality of packet destinations.

Abstract: A pipelined instruction dispatch or grouping circuit allows instruction dispatch decisions to be made over multiple processor cycles. In one embodiment, the grouping circuit performs resource allocation and data dependency checks on an instruction group, based on a state vector which includes representation of source and destination registers of instructions within said instruction group and corresponding state vectors for instruction groups of a number of preceding processor cycles.

Abstract: A system for providing a floating point square root comprises an analyzer circuit configured to determine a first status of a first floating point operand based upon data within the first floating point operand. In addition, the system comprises a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the square root of the first floating point operand and a resulting status embedded within the resulting floating point operand.

Abstract: A method for creating a histogram that includes identifying a lower extreme range counter and an upper extreme range counter for a plurality of data elements. The method further includes incrementing a value counter when the value counter corresponds to a value of a first data element in the plurality of data elements and incrementing the lower extreme range counter when a value of a second data element in the plurality of data elements is less than a pre-defined lower boundary. The method further includes incrementing the upper extreme range counter when a value of a third data element in the plurality of data elements is greater than a pre-defined upper boundary. The method further includes creating the histogram from the value counter, the lower extreme range counter, and the upper extreme range counter.

Abstract: A method of verifying the identity of a user by comparing a biomorphic sample from the user with a stored biomorphic pattern of the user, without access to an online database of encoded biomorphic patterns. An authorization process receives an encoded biomorphic pattern from the user, the encoded biomorphic pattern stored on a storage device containing a processor. The processor is powered by a device capable of reading the storage device. The authorization process verifies the encoded biomorphic pattern is a valid biomorphic pattern with a valid expiration date, and compares the encoded biomorphic pattern on the storage device to a biomorphic sample provided by the user, in order to grant access to the user. If an online database is available, authorization process transmits the result to the online database and receives, in return, an updated expiration date. The authorization process updates the storage device with the updated expiration date.

Abstract: A cord retaining apparatus includes a receptacle for receiving a head of a cord. A brack is mounted near the receptacle including an upper stop. An arm is pivotally attached to the bracket. A first length of the arm extends distal from the receptacle and a second length of the arm is substantially perpendicular to the first length. The arm is movable into and out of a position in which the second length is behind the head of the cord preventing removal of the cord. The upper stop prevents the arm from moving into a position where the arm does not naturally fall into the position behind the head of the cord.

Abstract: In one embodiment, a processor includes an execution unit configured to execute one or more threads and a detection unit coupled to detect whether a given thread includes an identifier. The execution unit is further configured to selectively continue execution of the given thread depending upon whether the detection unit detects the identifier.

Abstract: The present invention provides a method and apparatus for increased efficiency for translation lookaside buffers by collapsing redundant translation table entries into a single translation table entry (TTE). In the present invention, each thread of a multithreaded processor is provided with multiple context registers. Each of these context registers is compared independently to the context of the TTE. If any of the contexts match (and the other match conditions are satisfied), then the translation is allowed to proceed. Two applications attempting to share one page but that still keep separate pages can then employ three total contexts. One context is for one application's private use; one of the contexts is for the other application's private use; and a third context is for the shared page. In one embodiment of the invention, two contexts are implemented per thread. However, the teachings of the present invention can be extended to a higher number of contexts per thread.

Abstract: A pulse circuit contains an input stage configured to receive input pulses on input nodes using push-pull elements, wherein a given push-pull element is configured to receive an input pulse on a given input node and to provide a corresponding internal signal. The pulse circuit further contains a feedback loop that includes a logic element coupled between outputs from the push-pull elements and reset nodes of the push-pull elements. This logic element is configured to provide one or more outputs from the pulse circuit and to reset the internal signals from the push-pull elements via the feedback loop.

Abstract: Methods and systems consistent with the present invention provide distributed storage systems that are scalable, secure, available, and manageable. These storage systems may utilize a single storage switch and allow resource sharing while securely separating customer data. A snapshot capability may be provided to capture a point-in-time image of the stored data and to track changes made to the stored data relative to a point-in-time image.

Abstract: A system for cooling a semiconductor device is disclosed. The system includes a lid encasing the semiconductor device, a first plurality of carbon nanotubes disposed within the lid, and a fluid system configured to pass a fluid through the lid. Furthermore, a second system for cooling a semiconductor device is disclosed. The second system includes a lid, a first plurality of carbon nanotubes disposed within the lid, and a fluid system configured to pass a fluid through the lid. The lid is configured to be mounted over and encase the semiconductor device. Additionally, a method for cooling a semiconductor device is disclosed. The method includes disposing a first plurality of carbon nanotubes within a lid, mounting the lid over the semiconductor device, and passing a fluid through the lid.

Abstract: A garbage collector treats a heap as divided into regions. From a candidate set of those regions, it selects the collection sets on which it performs collection increments from among those regions in accordance with a selection criterion separate from the ages of the objects that those regions contain. It nonetheless segregates objects according to age, placing objects in such a manner that no candidate-set region containing an object whose age is less than some predetermined maximum also contains an object of a different age.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention provide for access control over dynamic intellectual capital content. A subscriber subscribes to a datatype, the datatype having a predetermined runtime property that restricts use of the datatype. The datatype is associated with a data referenced in the datatype and maintained separate from the datatype. The datatype is received responsive to the subscription. A determination is made whether the runtime properties are valid. If the runtime properties are valid, a determination is made whether a user of the subscriber has permission to access the data referenced in the datatype. If the user has permission to access the data, the user is provided access to the data.

Abstract: The invention involves a method for aggregating data in a distributed system. The method includes specifying an aggregation scope including a plurality of nodes, where the plurality of nodes includes a destination node and a plurality of non-destination nodes. The method also includes defining an aggregation tree for the plurality of nodes using at least one Distributed Hash Table, where the destination node is the root of the aggregation tree and where each of the plurality of non-destination nodes is one selected from a group of an interior node and a leaf node in the aggregation tree. The method also includes determining a final aggregation result for the aggregation tree using an aggregation function and aggregation data stored on the destination node and the plurality of non-destination nodes.

Abstract: A method including obtaining an operational status of a first processor core, where the first processor core is associated with a plurality of processor cores located on a chip; configuring a first IO block of a package design based on the operational status of the first processor core, where the package design is based on a fully functional chip; and configuring a stackup of the package design after configuring the first IO block for use with the chip.

Abstract: A method and apparatus for dynamically arbitrating, in hardware, requests for a resource shared among multiple clients. Multiple data streams or service requests require access to a shared resource, such as memory, communication bandwidth, etc. A hardware arbiter monitors the streams' traffic levels and determines when one or more of their arbitration weights should be adjusted. When a queue used by one of the streams is filled to a threshold level, the hardware reacts by quickly and dynamically modifying that queue's arbitration weight. Therefore, as the queue is filled or emptied to different thresholds, the queue's arbitration weight rapidly changes to accommodate the corresponding client's temporal behavior. The arbiter may also consider other factors, such as the client's type of traffic, a desired quality of service, available credits, available descriptors, etc.

Abstract: The present disclosure involves reconfigurable circuits that include an asynchronous data path with asynchronous control and at least one logic element coupled with the asynchronous data path that allows the circuit to be configured to more than one logical implementation through data and control token. In one particular example, the asynchronous data path with asynchronous control includes an interconnection of memory elements, such as latches, with each memory element including a corresponding asynchronous control element, such as a GasP element. One or more logical elements are coupled at one or more points of the data path, such coupling may involve feed-back, feed-forward, or combinations of both, and may include external data connections. Through distribution of data items and control tokens to the asynchronous data path with asynchronous control, the fixed logical coupling to the data path may be reconfigured to provide various logical arrangements.

Abstract: One embodiment of the present invention provides an integrated circuit module. This module includes a semiconductor die with an active face, upon which active circuitry and signal pads reside, and a back face opposite the active face. The module uses a flexible cable to deliver electrical power to the active face of the semiconductor die from a power distribution board located above the active face of the semiconductor die. This flexible cable provides electrical power to the semiconductor die without interfering with the alignment and heat removal functions of the module.

Abstract: In a method for determining capacitance, a first time-varying signal is driven on a first terminal of a first capacitor and a second time-varying signal is driven on a first terminal of a second capacitor, where the first time-varying signal and the second time-varying signal have a pre-determined phase relationship with each other. These signals are received on second terminals of the first capacitor and the second capacitor and demodulated using a periodic signal to produce demodulated signals. This periodic signal has the same fundamental frequency as the first time-varying signal and the second time-varying signal. A DC component in the demodulated signals is then determined by filtering the demodulated signals, and the sign of the DC component is used to determine a relative capacitance of the first capacitor and the second capacitor.