Abstract: A method for reading data from a memory module over a bi-directional bus is provided. The method initiates with writing data into a storage element asynchronously according to a first clock domain. Next, the data is read from the storage element synchronously according to a second clock domain. A microprocessor and a system wherein data is read over a bi-directional bus are included.

Abstract: One embodiment of the present invention provides a system for operating a key distribution center (KDC) that provides keys to facilitate secure communications between clients and servers across a computer network, wherein the system operates without having to store long-term server secrets. The system operates by receiving a communication from a server at the KDC. This communication includes an identifier for the server, as well as a temporary secret key to be used in communications between a client and the server for a limited time period. In response the communication, the system attempts to authenticate the server. If the server is successfully authenticated, the system stores the temporary secret key at the KDC, so that the temporary secret key can be subsequently used to facilitate communications with the server.

Abstract: A method of tuning a test trace that is capacitively coupled to a number of signal traces. A method for determining a configuration of a device comprising signal traces and a capacitively coupled test trace may include selecting a test frequency of a test signal to be driven on selected signal traces during a test mode of device operation, and tuning circuit characteristics of the test trace to generate a bandpass frequency response including a passband and a stopband, where a detection frequency corresponding either to the test frequency or a selected harmonic of the test frequency is included in the passband. Tuning of circuit characteristics may include selecting a degree of capacitive coupling between the test trace and the signal traces such that, within a specified constraint for signal degradation on the signal traces, the bandpass frequency response of the given test trace satisfies a specified transmission requirement at the detection frequency.

Abstract: We explore techniques for designing nonblocking algorithms that do not require advance knowledge of the number of processes that participate, whose time complexity and space consumption both adapt to various measures, rather than being based on predefined worst-case scenarios, and that cannot be prevented from future memory reclamation by process failures. These techniques can be implemented using widely available hardware synchronization primitives. We present our techniques in the context of solutions to the well-known Collect problem. We also explain how our techniques can be exploited to achieve other results with similar properties; these include long-lived renaming and dynamic memory management for nonblocking data structures.

Abstract: System and method for submitting and performing computational tasks in a distributed heterogeneous networked environment. Embodiments may allow tasks to be submitted and run in parallel on a network of heterogeneous computers implementing a variety of operating environments. In one embodiment, a user on an originating node may advertise code on the network. Peer nodes that respond to the advertisement may receive the code. A job to be executed by the code may be split into separate tasks to distributed to the peer nodes that received the code. These tasks may be advertised on the network. Tasks may be assigned to peer nodes that respond to the task advertisements. The peer nodes may then work on the assigned tasks. Once a peer node's work on a task is completed, the peer node may return the results of the task to the originating node.

Abstract: A floating point unit generates results in which status information generated for an operation is encoded within the resulting operand, instead of requiring a separate floating point status register for the status information. In one embodiment, a floating point operand data structure includes a first portion having floating point operand data and a second portion having embedded status information associated with at least one status condition of the operand data. The status condition may be determined from only the embedded status information. The status condition may also be associated with at least one floating point operation that generated the operand data structure. The outcome of a conditional floating point instruction may be based on the embedded status information without regard to contents of the floating point status register.

Abstract: A method for tracing an instrumented program on a system during booting, including loading object code defining enabling information into a property file associated with a tracing framework, rebooting the system, processing the property file to enable the tracing framework, wherein enabling the tracing framework comprises creating an anonymous consumer state, and tracing the instrumented program using the enabled tracing framework.

Abstract: A transactional memory implementation has been developed that is capable of coordinating concurrent hardware transactional memory (HTM) and software transactional memory (STM) transactions over a unified transactional memory space. Some implementations employ hardware transactional memory, if available or suitable, to improve performance. Some exploitations include a hardware transactional memory in which, or for which, hardware-mediated transactions are augmented to include within their transactional scope (or mechanism) one or more additional transactional locations that facilitate coordination with concurrently executing software-mediated transactions (if any).

Abstract: A technique for improving the performance of a system that supports simultaneous multi-threading (SMT). When a first thread encounters a halt sequence, the system starts a transactional memory operation by generating a checkpoint and entering a transactional-execution mode. Next, the system loads from a mailbox address associated with the halt sequence. The system then stalls execution of the first thread, so that the first thread does not execute instructions within the halt sequence, thereby freeing up processor resources for other threads. To terminate the halt sequence, a second thread stores to the mailbox address, which causes a transactional-memory mechanism within the processor to detect an interference with the previous load from the mailbox address by the first thread and which causes the first thread to exit from the halt sequence. The system then continues executing instructions following the halt sequence.

Abstract: A service discovery mechanism may allow clients in a distributed computing environment to search for services. The service discovery mechanism may allow a client to request a capability credential from a service. The distributed computing environment may include a mechanism for a client to negotiate service access rights and to then obtain a capability credential that may be used to obtain the service's access interface to the set or subset of the service's capabilities that were requested or negotiated by the client. In one embodiment, the client may present to the service a set of desired capabilities. The service may then respond with a capability credential that may convey to the client the rights to use the requested capabilities. A complete service advertisement may be needed to create a message endpoint for accessing the service. In an embodiment, the capability credential may be used by a client to obtain a complete advertisement for only the requested or negotiated capabilities.

Abstract: One embodiment of the present invention provides a system that facilitates detecting and correcting errors. The system operates by receiving a data packet comprised of p words on a communication pathway, wherein each bit of a word is received on a separate data line in a set of data lines that comprise the communication pathway. The system also receives a time signature t on the communication pathway, wherein t contains per-bit error information for the p words in the data packet. As the data packet is received, the system performs an error-detection operation on each data bit of the data packet in parallel, wherein the error-detection operation generates per-bit error information for each bit position across the p words in the data packet. Finally, the system compares the generated per-bit error-information with the corresponding per-bit error information in the time signature t to determine if there exists an error.

Abstract: A method for managing an application server that is configured to execute a plurality of test applications is provided. The method includes the operations of (a) processing a first one of the plurality of test applications, (b) determining if the first application fails to be processed to completion, (c) recording an exception identifying an explanation for the failure if the first test application fails to be processed to completion, (d) refreshing the application server, (e) executing a next one of the plurality of test applications, and (f) repeating operations (a) through (e) if there are remaining ones of the plurality of test applications that still need to be processed.

Abstract: A small footprint device can securely run multiple programs from unrelated vendors by the inclusion of a context barrier isolating the execution of the programs. The context barrier performs security checks to see that principal and object are within the same namespace or memory space and to see that a requested action is appropriate for an object to be operated upon. Each program or set of programs runs in a separate context. Access from one program to another program across the context barrier can be achieved under controlled circumstances by using a global data structure.

Abstract: A method and apparatus performs computer application level testing of an instruction cache in multi-processor or multi-core systems. Instruction cache cannot be written to and read from directly. Thus, one microprocessor core is utilized to perform application level testing of an instruction cache of another microprocessor core. The method and apparatus uses two software threads: a controller thread and a target thread. The target thread uses a portion of the instruction cache as a scratch pad for synchronization with the controller thread. The controller thread controls the sequence of operations to perform a March test on the target instruction cache.

Abstract: In general, the invention relates to a method for routing a packet. The method includes receiving the packet in a network interface card (NIC), classifying the packet, placing the packet in a receive ring of the NIC, sending the packet to a virtual NIC associated with the receive ring, sending the packet to a first container associated with the virtual NIC, and routing the packet to a packet destination using the first container.

Abstract: A method for configuring a network on a host includes obtaining a first virtual network stack and a second virtual network stack on the host, configuring a first transport layer implementation on the first virtual network stack, configuring a second transport layer implementation on the second virtual network stack, receiving a packet by the host, sending a packet to the first virtual network stack, and processing the packet using the first transport layer implementation.

Abstract: A method for routing a packet. The method includes receiving the packet from a first network into a network interface card (NIC), where the NIC is operatively connected to a host and the host includes a first virtual network stack and a second virtual network stack. The method further includes sending the packet to a first virtual network stack, where the first virtual network stack includes a first filter, a first network layer, and a first transport layer. In addition, the first filter, the first network layer, and the first transport layer are isolated from the second virtual network stack. If the packet is permitted through the first filter in the first virtual network stack, then the packet is sent to a first virtual NIC.

Abstract: A data storage device is disclosed with a housing sized for a tape drive. A tape reel is mounted for rotation within the housing and a guide is mounted in the housing spaced apart from the tape reel. A first end of a data tape segment is mounted to the tape reel and a second end is not mounted to the tape reel. A structural tape segment has a pair of ends mounted between the first and second ends of the data tape segment for structurally enhancing an intermediate region of the data tape segment. In another embodiment, a structurally enhanced intermediate region is advanced to a read/write region of the data storage device during storage of the device for preventing inadvertent damage to the data tape.

Abstract: A method and system of processing a cryptographic packet includes receiving a first cryptographic packet in a host CPU. A first set of data required to execute the first cryptographic packet is identified. The first cryptographic packet and the required first set of data is transferred to a cryptographic co-processor. The first cryptographic packet is executed in the cryptographic co-processor. The host CPU is notified that the execution of the first cryptographic packet is complete. The executed first cryptographic packet is received in the host CPU.

Abstract: One embodiment of the present invention provides a system that optimizes synchronization between monitored signals in a computer system. During operation, the system receives a number of monitored signals. The system then forms a number of signal pairs by grouping each signal with every other signal. Next, the system optimizes synchronization between the signals by iteratively perturbing the timing of each signal in an attempt to increase the value of an objective function which reflects the overall synchronization between all the signals.