Abstract: One embodiment of the present invention provides a system that facilitates delayed block allocation in a distributed file system. During operation, the system receives a write command at a client, wherein the write command includes a buffer containing data to be written and a file identifier. In response to receiving the write command, the system reserves a set of disk blocks for the file from a virtual pool of disk blocks allocated to the client. The system also transfers the data to be written to the kernel of the client where the data waits to be transferred to the disk.

Abstract: A system and method for performing speculative writestream transactions in a computing system. A computing system including a plurality of subsystems has a requesting subsystem configured to initiate a writestream ordered (WSO) transaction to perform a write operation to an entire coherency unit by conveying a WSO request to a home subsystem of the coherency unit. The requester is configured to perform the write operation without first receiving a copy of the coherency unit and complete WSO transactions initiated in the order in which they are initiated. The home subsystem is configured to process multiple WSO transactions directed to a given coherency unit in the order in which they are received. When the requester initiates a WSO transaction to a given coherency unit, the coherency unit is locked. Responsive to receiving the WSO request, the home subsystem conveys a pull request for the write data to the requester.

Abstract: One embodiment of the present invention provides a system which performs a constrained optimization of circuit parameters. During operation, the system selects two circuit parameters associated with a circuit path, wherein the optimization is to be performed on the first circuit parameter while a limitation on second circuit parameter functions as a constraint on the optimization of the first circuit parameter. Next, the system generates objective functions which model the first circuit parameter and the second circuit parameter in terms of logical effort. The system then uses the objective functions to generate a constraint expression, wherein the constraint expression mathematically relates the optimization of the first circuit parameter to the constraint on the second circuit parameter. Next, the system computes a trade-off curve using the constraint expression. The system then computes transistor sizes for the circuit path based on a selected point from the trade-off curve.

Abstract: An application identifier (AID) for an application installed on a smart card comprises a registered application provider identifier (RID). The AID may be processed by determining the RID for an application from the AID of the application, generating an identifier for a network resource from the RID, transmitting a request to the network resource using the identifier, and receiving a response to the request. The response comprises material for use in handling the application on the smart card.

Abstract: The analysis of the lifetime of objects in a garbage-collected system may be accomplished quickly and effectively using reference counts and cyclic garbage analysis. A reference count is maintained for each of the objects to indicate the number of incoming pointers. Each time the graph structure is altered, the reference counts are updated. Timestamps are recorded each time the reference count for objects change. If a reference count goes to zero, the corresponding object may be indicated as dead. A garbage collection need only be run once (perhaps at the end), and after it is run the system may indicate which objects are cyclic garbage. The timestamps for objects which are cyclic garbage are then reviewed in reverse chronological order. For each timestamp found, the corresponding object and any object reachable from the corresponding object are indicated as dead. These objects are then removed from the set of cyclic garbage.

Abstract: A switch chassis includes a plane having pass-through vias. An array of connector pairs is provided. A connector pair includes a first multi-path connector on first side of the plane and a second multi-path connector on the second side of the plane interconnected through the pass-through vias in the plane. Fabric cards can be connected to respective columns of first connectors and line cards can be connected respective rows of second connectors of the connector pairs to orient the fabric and lines cards orthogonally with respect to each other.

Abstract: A cable management system provides cable management for a switch chassis configured to receive a plurality of line card units. The cable management system comprises a cable guide arrangement configured to guide each of a plurality of cables from a line card such that the cables extend out from the line card unit and lie substantially within a plane.

Abstract: A method for performing a cryptographic function including calling into an encryption framework to perform the cryptographic function, wherein calling into the encryption framework comprises sending a request to perform the cryptographic function from a kernel consumer, and processing the request and returning the result to the kernel consumer, wherein processing the request comprises determining whether the request is synchronous or asynchronous, and determining which cryptographic provider to use to perform the cryptographic function.

Abstract: In one embodiment, a node for a multi-node computer system comprises a coherence directory configured to store coherence states for coherence units in a local memory of the node and a coherence controller configured to receive a coherence request for a requested coherence unit. The requested coherence unit is included in a memory region that includes at least two coherence units, and the coherence controller is configured to read coherence states corresponding to two or more coherence units from the coherence directory responsive to the coherence request. The two or more coherence units are included in a previously-accessed memory region, and the coherence controller is configured to provide the requested coherence unit with a predicted coherence state responsive to the coherence states in the previously accessed memory region.

Abstract: A multiply execution unit that can generate the integer product of a multiplicand and a multiplier and is also operable to generate the XOR product of the multiplicand and the multiplier. The multiply execution unit includes a summing circuit for summing a plurality of partial products. The summing circuit includes a plurality of rows. The summing circuit can generate an integer sum of the plurality of partial products and can generate an XOR sum of the plurality of partial products. The summing circuit includes a plurality of compressors in the first row of the summing circuit. The plurality of compressors each has more than three inputs that receive data, a carry output, and a sum output.

Abstract: An apparatus and method for floating point exception prediction and recovery. In one embodiment, a processor may include instruction fetch logic configured to issue a first instruction from one of a plurality of threads and to successively issue a second instruction from another one of the plurality of threads. The processor may also include floating-point arithmetic logic configured to execute a floating-point instruction issued by the instruction fetch logic from a given one of the plurality of threads, and further configured to determine whether the floating-point instruction generates an exception, and may further include exception prediction logic configured to predict whether the floating-point instruction will generate the exception, where the prediction occurs before the floating-point arithmetic logic determines whether the floating-point instruction generates the exception.

Abstract: In one embodiment, a method and apparatus for minimizing unload times in a tape drive system is disclosed. The method includes: writing to a tape in serpentine format; reaching a comparison point on the tape, wherein at the comparison point an actual capacity is compared to an expected capacity; utilizing the comparison at the comparison point to estimate a distance from the comparison point until a guaranteed capacity for the tape is reached; and determining a turn-around point on the tape based on the estimated distance, wherein at the turn-around point a tape drive writing to the tape to stop writing in a first direction and then continue writing in a second direction opposite from the first direction and towards a physical beginning of the tape. Other embodiments are also disclosed.

Abstract: In one general aspect, a network communication unit is disclosed that includes a cryptographic record parsing offload engine that has an input and an output. The unit also includes a processor that includes cryptographic handshake logic and has an input operatively connected to the output of the cryptographic record parsing offload engine.

Abstract: A method and apparatus for determining a stack distance histogram for running software. The method may include receiving a plurality of memory references each including a corresponding address. The method may also include performing a first hash function and a second hash function on each received address. In addition, the method may include selectively storing an indication representative of each corresponding address in a hash table dependent upon results of the first hash function and the second hash function. A stack distance may then be determined based upon contents of the hash table.

Abstract: A system for developing and using a request for transaction framework including a framework engine configured to enable a market maker to develop a request for transaction for a particular market, and a request for transaction engine configured to enable an organization within the relevant market to prepare a request for transaction relating to a resource requirement and select a response relating to the resource requirement. In a preferred embodiment, the market maker creates a request for transaction framework by manipulating attribute parameters and identifying an analysis framework. A request for transaction framework may be a request for proposal framework, a request for quote framework, or other type of framework in which there is a request followed by a plurality of responses and a selection of one of the responses.

Abstract: A clock circuit. The clock circuit includes a phase detector and an output unit. The phase detector is coupled to receive a reference clock signal and an output clock signal, and is configured to provide a phase signal indicative of a phase difference between the reference and output clock signals. The output unit is configured to provide the output clock signal, and is coupled to a first supply voltage node and a second supply voltage node. The output unit includes a biasing circuit and a voltage-controlled element. The biasing circuit is coupled to receive a control voltage based on the phase signal and is configured to generate a bias voltage based on the received control voltage. The voltage-controlled element is configured to adjust a parameter of the output clock signal based on the bias voltage. A supply-independent output clock is attained using this configuration.

Abstract: System and method for proxying isomorphic interfaces in different subsystems. Embodiments may provide a proxy mechanism that may generate proxies for isomorphic interfaces at runtime. Embodiments may allow two mutually indifferent subsystems to communicate with each other in a straightforward, transparent manner via proxies, without requiring a common shared library or complex coding. Embodiments of the proxy mechanism transparently generate proxies for isomorphic interfaces between subsystems in a virtual machine. In one embodiment, the application developer registers the interfaces that require proxying. The proxy mechanism then generates proxy instances. Methods may then be invoked, and the proxies handle the details of converting and forwarding the calls in accordance with the appropriate interface.

Abstract: One embodiment of the present invention provides a system that improves the effectiveness of prefetching during execution of instructions in scout mode. During operation, the system executes program instructions in a normal-execution mode. Upon encountering a condition which causes the processor to enter scout mode, the system performs a checkpoint and commences execution of instructions in scout mode, wherein the instructions are speculatively executed to prefetch future memory operations, but wherein results are not committed to the architectural state of a processor. During execution of a load instruction during scout mode, if the load instruction is a special load instruction and if the load instruction causes a lower-level cache miss, the system waits for data to be returned from a higher-level cache before resuming execution of subsequent instructions in scout mode, instead of disregarding the result of the load instruction and immediately resuming execution in scout mode.

Abstract: One embodiment of the present invention provides a system that implements a hash table that is fully dynamic and lock-free. During a lookup in the hash table the system first uses a hash key to lookup a bucket pointer in a bucket array. Next, the system follows the bucket pointer to a data node within a linked list that contains all of the data nodes in the hash table, wherein the linked list contains only data nodes and at most a constant number of dummy nodes. The system then searches from the data node through the linked list to locate a node that matches the hash key, if one exists.

Abstract: The present invention is an apparatus and method for increasing the amount of data on a transmission path on a printed circuit board. Conventional methods allow only one data signal to be transmitted on the transmission path. The present invention uses multiple transmitters to modulate multiple data signals to form multiple modulated signals. The modulated signals are transmitted, possibly simultaneously, on the transmission path to receivers configured to demodulate individual modulated signals and recover the original data signals.