Abstract: Apparatus for monitoring transient events in a power supply line the apparatus comprising a transient hold circuit having an input and an output wherein said input is arranged to be connected to said power supply line; and arranged to present at least one of a maximum and a minimum power value at said output; a time module adapted to allocate a time stamp to a detected power transient presented at said output; and a memory for storing said power transient and said corresponding time stamp.

Abstract: A method for storing data, including receiving a request to store data in a storage pool, determining a quantized deadline for the request, placing the request in an Input/Output (I/O) queue using the quantized deadline, and issuing the request to the storage pool using the I/O queue.

Abstract: A method for emulating a system call includes making the system call by a first process in a first operating system (OS) for interacting with a second process, wherein the first OS is emulated in a second OS, spawning an agent process, wherein the agent process is a child process of the first process, implementing a functionality of the system call using a general mechanism in the second OS between the agent process and the second process, passing a result associated with the system call from the second process to the agent process using the general mechanism, and relaying the result from the agent process to the first process using a system call in the second OS, wherein the result is stored by the first process.

Abstract: A method for recommending music that includes identifying a granularity of a plurality of genres based on a request for music similarity, wherein the request identifies a user, training a genre classifier based on the granularity to obtain a trained genre classifier, calculating a first profile by the trained genre classifier, wherein the first profile that includes, for each of the plurality of genres, the likelihood that a music selection associated with a user is in the genre, calculating a second profile by the trained genre classifier, wherein the second profile that includes, for each of the plurality of genres, the likelihood that an unknown music selection is in the genre, obtaining a first similarity score between the first profile and a second profile, and recommending the unknown music selection to the user based on the first similarity score.

Abstract: In the distributed enterprise application integration system, modularized components located on multiple hosts are centrally managed so as to facilitate communication among application programs. Collaboration services traditionally associated with a central server, such as, for example, message queues, message publishers/subscribers, and message processes, are instead distributed to multiple hosts and monitored by a central registry service. This system allow configuration management to be performed in a central location using a top-level approach, while implementation and execution tasks are distributed and delegated to various components that communicate with the applications.

Abstract: One embodiment of the present invention provides a system that facilitates phase-buffering on a bit-by-bit basis using a control queue. The system includes a control queue, wherein a stage in the control queue is configured to accept both a first control signal and a second control signal, wherein the first control signal and the second control signal are mutually exclusive, wherein the first control signal being asserted indicates the value of a corresponding bit is zero, while the second control signal being asserted indicates the value of the corresponding bit is one. A forward-transfer mechanism couples the first control signal or the second control signal from the input of the stage through storage elements to the output of the stage. A reverse transfer mechanism accepts an acknowledgement signal at the output of the stage and transfers the acknowledgement signal through a storage element to the input of the stage.

Abstract: In one embodiment, a processor comprises a plurality of instruction buffers, an instruction cache coupled to supply instructions to the plurality of instruction buffers, and a cache miss unit coupled to the instruction cache. Each of the plurality of instruction buffers is configured to store instructions fetched from a respective thread of a plurality of threads. The cache miss unit is configured to monitor cache misses in the instruction cache. Particularly, the cache miss unit is configured to detect which of the plurality of threads experience a cache miss to a cache line. Responsive to a return of the cache line for storage in the instruction cache, the cache miss unit is configured to concurrently cause at least one instruction from the cache line to be stored in each of the plurality of instruction buffers that corresponds to one of the plurality of threads which experienced the cache miss to the cache line.

Abstract: In one embodiment, a processor comprising at least one translation lookaside buffer (TLB) and a control unit coupled to the TLB. The control unit is configured to track whether or not at least one update to the TLB is pending for at least one of a plurality of strands. Each strand comprises hardware to support a different thread of a plurality of concurrently activateable threads in the processor. The strands share the TLB, and the control unit is configured to delay a demap operation issued from one of the estrands responsive to the pending update, if any.

Abstract: A storage virtualization environment is provided that includes a network switch system for initializing a virtual volume in a system including a host system, and storage devices. The network switch system includes storage processors including first and second tier storage processors and a Virtualization Coherency Manager (VCM) for receiving storage connectivity identifying which storage processors are connected to selected ones of the storage devices. Further, the network switch system includes a master storage processor for creating a logical tree based on the storage connectivity information, the logical tree reflecting a virtual volume of data distributed across the storage devices and includes (i) first tier objects representing partitions of the virtual volume data and (ii) second tier objects representing a logical configuration of the virtual volume.

Abstract: A system including a memory, a first processor operatively connected to a first cache, a second processor operatively connected to a second cache, a directory implemented in hardware operatively connected to the first cache, the second cache, and the memory, wherein the directory comprises at least one location, and wherein the at least one location is configured to store a first entry and a second entry.

Abstract: One embodiment of the present invention provides a system that facilitates scheduling packets in a multi-service integrated switch fabric wherein packet services are attached directly to the switch fabric. During operation, the system receives a packet at the switch fabric. Upon receiving the packet, the system uses pre-defined rules to identify packet services to perform operations on the packet. The system then attaches a tag to the packet, which identifies the packet services to be performed on the packet. The system then schedules the packet on the switch fabric. During the scheduling process, the system considers the packet services identified by the tag and the occupancies of queues associated with the identified packet services when scheduling the packet in an attempt to optimize network throughput.

Abstract: Prefetch information is generated for multi-block indirect memory access chains. A method may include selecting a chain of indirect memory accesses of a procedure, the chain comprising a head access that does not depend for its address on another prefetch candidate memory access within the procedure and an indirect access that depends for its address on the head access. The method may further include determining a prefetch-ahead value for the chain, and generating a load operation corresponding to the head access that specifies a target memory address that is dependent upon the prefetch-ahead value and an address of the head access. The method may further include, for a terminal indirect access of the chain, generating a respective prefetch operation that is dependent for its address computation on results of preceding load operations in the same manner as its corresponding terminal indirect access depends upon preceding accesses in the chain.

Abstract: Embodiments of a decentralized, distributed trust mechanism that may be used in peer-to-peer platforms, to implement trust relationships based on data relevance between peers on a network and to implement trust relationships between peers and content and data (codat). In one embodiment, the trust mechanism may provide a trust spectrum of multiple levels wherein unique peer identities may be established to enable authentication and the assignment of the peers' associated access policies within a peer group. In one embodiment, the trust spectrum may have Certificate Authority signed certificates as a maximum level of security, and self-signed certificates as a minimum level of security. Since a certificate is one form of codat, in one embodiment the trust mechanism may be applied to a peer group member's collection of signed certificates for a given peer group.

Abstract: A method and system for identifying multi-block indirect memory access chains. A method may include identifying basic blocks between an entry point and an exit point of a procedure, where the procedure includes a control statement governing its execution. It may be determined whether a probability of execution of a given basic block relative to the control statement equals or exceeds a first threshold value. If so, a respective set of one or more chains of indirect memory accesses may be generated, where each chain includes at least a respective head memory access that does not depend for its memory address computation on another memory access within the given basic block. Chains may be joined across basic blocks dependent upon whether the relative execution probabilities of the blocks exceed a threshold value.

Abstract: A system for implementing a super-user-compatible privilege security policy on a computer operating system is disclosed. The system includes a kernel for enforcing a security policy on processes, based on privileges. The system also includes a privilege model that interfaces with the kernel and implements a framework in which super-user based processes and privilege based processes transparently interface with the kernel. The privilege model includes several privilege sets associated with each process, a privilege awareness property state associated with each process, the property state indicating whether or not a process is privilege aware, and a software module for automatically modifying the privilege sets and the property state, on a per process basis, based on individual process behavior.

Abstract: A method and mechanism for producing and executing self-steering program code. A method comprises analyzing program code and identifying portions which may be amenable to optimization. Having identified such a portion of code, at least one optimized version of the identified code is added to the program code. Additionally, a selection mechanism is added to the program code which is configured to select between two or more versions of the portion of code during runtime. The modified program code is then compiled with the added optimized version and the selection mechanism. During execution, monitoring of behavior of the code may be enabled or disabled. Based upon such monitored behavior, a different version of the code may be selected for execution.

Abstract: In general, in one aspect, the invention relates to a computer readable medium comprising executable instructions for verifying generation of an intermediate representation (IR). The generation of the IR is verified by generating the IR from source code and interpreting the IR to obtain an interpretation result. Interpreting the IR includes encountering a method call in the IR, locating an execution unit corresponding to the method call, executing the execution unit to obtain an execution result, replacing a portion of the IR with the execution result to obtain a reduced IR, and obtaining the interpretation result from the reduced IR. Finally, the interpretation result is compared to an expected result of the source code, wherein the generation of the IR is verified if the interpretation result equals the expected result.

Abstract: Transactional programming promises to substantially simplify the development and maintenance of correct, scalable, and efficient concurrent programs. Designs for supporting transactional programming using transactional memory implemented in hardware, software, and a mixture of the two have emerged recently. However, various features and capabilities that would be desirable for debugging programs executed using transactional memory are absent from conventional debuggers. Because transactional memory implementations provide the “illusion” of multiple memory locations changing value atomically, while in fact they do not, there can be significant challenges involved with integrating debuggers with such programs to provide the user with a coherent view of program execution. We describe use of transactional memory access tracking mechanism for implementations of watchpoints on memory locations that correspond to transactional variables.

Abstract: A movable data center is disclosed that comprises a portable container in which an operable computer system is assembled. A data link, power supply link and cooling system are provided through ports on the exterior of the container. The computer system is assembled to a rack that is secured to the container with a shock absorbing mechanism.

Abstract: A data space profiler may include a graphical user interface (GUI) for sorting, aggregating and displaying profile data associated with runtime events of a profiled software application. This profile data may include costs associated with events as well as extended address elements and other code behavior attributes associated with them. The GUI may include means for selecting a perspective from which cost data is to be presented as well as presentation options for displaying the data. The presentation options may include panning and zooming options, which may determine how the data is sorted and/or aggregated for display. The GUI may also include means for specifying filter criteria, which may be used to determine which data to display. By providing means to alternate the display of profile data according to different perspectives and filtering criteria, the GUI may facilitate identification of performance bottlenecks of the profiled application and the causes thereof.