Abstract: An electronic device includes multiple IC dies stacked in an offset stacking arrangement on a substrate. Each IC die includes electrically isolated step pads that facilitates transmitting a dedicated signal between a (beginning) substrate bonding pad and a selected (terminal) contact pad of any die by way of short bonding wires that extend up the stack between the electrically isolated step pads. A memory devices includes stacked memory IC die, wherein “shared” signal transmission paths are formed by associated bonding wires that link corresponding contact pads of each memory die, and dedicated select/control signals are transmitted to each memory die by separate transmission paths formed in part by associated electrically isolated step pads. Substrate space overhung by the stack is used for passive components and IC dies. Memory controller die may be mounted on the stack and connected by dedicated transmission paths utilizing the electrically isolated step pads.

Abstract: A USB device including a housing and a rear cap that is rotatably connected to the housing to facilitate deploying and retracting a plug connector through a front opening of the housing. The plug connector is fixedly connected onto the front end of a sliding rack assembly that is disposed in housing such that the sliding rack assembly is slidable along a longitudinal axis. The sliding rack assembly includes a carrier including a carrier tray for supporting electronic devices and an elongated positioning rod extending from a rear portion of the carrier tray. The positioning rod is operably engaged with an actuator portion such that manual rotation of the rear cap relative to the housing around the longitudinal axis causes the sliding rack assembly to slide inside the housing between retracted and deployed positions.

Abstract: A flash-memory cache card caches data that a host writes to a hard disk drive. A flash-memory array has physical blocks of flash memory arranged into first and second data areas having M blocks each, and a wear-leveling-counter pool. An incoming logical sector address (LSA) from a host is mapped to one of M entries in a RAM lookup table using a hash of modulo M. The RAM entry stores a mapping to a physical block in a foreground area that is either the first or the second data area. Pages in the physical block are read for a matching LSA that indicates a cache hit. Full pages are written back to the hard disk and erased in the background while the other data area becomes the foreground area. A new physical block with a low wear-level count is selected from blocks in the new foreground area.

Abstract: A memory module assembly includes two-plate heat sink attached to one or more of the integrated circuits (e.g., memory devices) of a memory module PCBA by adhesive. The adhesive is either heat-activated or heat-cured. The adhesive is applied to either the memory devices or the heat-sink plates, and then compressed between the heat-sink plates and memory module using a fixture. The fixture is then passed through an oven to activate/cure the adhesive. The two heat sink plates are then secured by a clip to form a rigid frame.

Abstract: Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks.

Abstract: A USB device including a housing and a protective cap that are slidably and/or pivotably connected together such that the protective cap is able to slide and/or pivot between an open position, in which a plug connector extending from the front of the housing is exposed for operable coupling to a host system, and a closed position, in which the protective cap is disposed over the front end portion of the housing to protect the plug connector. A pivoting/sliding mechanism is provided on the housing and cap that secures the protective cap to the housing at all times, including during transitional movements of the protective cap between the opened and closed positions.

Abstract: Truncation reduces the available striped data capacity of all flash channels to the capacity of the smallest flash channel. A solid-state disk (SSD) has a smart storage switch salvages flash storage removed from the striped data capacity by truncation. Extra storage beyond the striped data capacity is accessed as scattered data that is not striped. The size of the striped data capacity is reduced over time as more bad blocks appear. A first-level striping map stores striped and scattered capacities of all flash channels and maps scattered and striped data. Each flash channel has a Non-Volatile Memory Device (NVMD) with a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory in the NVMD. Wear-leveling and bad block remapping are preformed by each NVMD. Source and shadow flash blocks are recycled by the NVMD. Two levels of smart storage switches enable three-level controllers.

Abstract: A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

Abstract: A case-grounded flash-memory drive has a printed-circuit board assembly (PCBA) with flash-memory chips and a controller chip. The PCBA is encased inside an upper case and a lower case, with a Serial AT-Attachment (SATA) connector that fits through and opening between the cases. The cases can be assembled with the PCBA by a snap-together, ultrasonic-press, screw-fastener, or thermal-bond adhesive method. Dual-axis case-grounding pins draw any electro-static-discharges (ESD) current off the upper case along a primary axis and onto a PCBA ground through a secondary axis washer that is screwed into the PCBA. The primary axis body of the dual-axis case-grounding pins fits around a PCBA notch while the secondary axis passes through a metalized alignment hole for grounding. When the SATA connector is inserted into a host, the host ground sinks ESD currents collected by the dual-axis case-grounding pins.

Abstract: A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

Abstract: A flash-memory device has a printed-circuit board assembly (PCBA) with a PCB with a flash-memory chip and a controller chip. The controller chip includes an input/output interface circuit to an external computer over a Secure-Digital (SD) interface, and a processing unit to read blocks of data from the flash-memory chip. The PCBA is encased inside an upper case and a lower case, with SD contact pads on the PCB that fit through contact openings in the upper case. Supporting end ribs under each of the SD contact pads and middle ribs support the PCB at a slanted angle to the centerline of the device. The PCB slants upward at the far end to allow more thickness for the chips mounted to the bottom surface of the PCB, and slants downward at the insertion end to position the SD contact pads near the centerline.

Abstract: A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.

Abstract: A cryogenic grinding mill for grinding organic base material pieces into sub-micron-sized powder particles. An upper grinding block is rotated relative to a stationary lower grinding block by a motor, and is maintained at a temperature below ?150° C. by a cryogenic system including an annular liquid nitrogen chamber disposed around the grinding blocks. The upper grinding block defines a trench for receiving base material pieces fed by a feed system, and includes through-holes that extend from the trench to a grinding region formed between the grinding surfaces of the upper and lower blocks. When the upper grinding block is rotated, the base material pieces are gravity-fed from the trench to the grinding region, and ground powder material is forced to a peripheral edge of the grinding region. The powder material is then filtered, and particles having an undesirably large size are fed back into the trench for re-grinding.

Abstract: ESD protection for a portable electronic device is provided by sandwiching a metal ground layer between prepreg (i.e., FR4 or other non-conductive PCB material) layers to form an ESD preventive PCB structure, where the metal ground layer is electrically connected to one or more of the integrated circuit (IC) components (e.g., at least one controller die, a non-volatile memory die, oscillator and passive components) that are mounted on the PCB by way of conductive via structures, and is accessible by way of one or more conductive anchor hole structures to external grounding structures. The one or more conductive anchor hole structures are positioned such that the metal ground layer is automatically electrically connected to the chassis ground of a host system when the portable device is coupled to a plug structure of the host system, e.g., by way of a metal connector jacket.

Abstract: A hybrid solid-state disk (SSD) has multi-level-cell (MLC) or single-level-cell (SLC) flash memory, or both. SLC flash may be emulated by MLC that uses fewer cell states. A NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Most data is block-mapped and stored in MLC flash, but some critical or high-frequency data is page-mapped to reduce block-relocation copying. A hybrid mapping table has a first-level and a second level. Only the first level is used for block-mapped data, but both levels are used for page-mapped data. The first level contains a block-page bit that indicates if the data is block-mapped or page-mapped. A PBA field in the first-level table maps block-mapped data, while a virtual field points to the second-level table where the PBA and page number is stored for page-mapped data. Page-mapped data is identified by a frequency counter or sector count. SRAM space is reduced.

Abstract: A pen-type computer peripheral device includes an elongated housing containing a PCBA having a plug connector. The PCBA is secured to a positioning member that is actuated by way of a press-push button that is exposed through a slot defined in a wall of the housing. A spring-loaded mechanism includes a spring and a locking mechanism that locks the connector in a retracted position and a deployed position, and the spring biases the connector from the retracted position to the deployed position, or vice versa.

Abstract: A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

Abstract: Embodiments of a plug and cap of a Universal-Serial-Bus (USB) device have been presented. In one embodiment, a USB device includes a main body, a piece of string, and a cap. The main body has a printed circuit board assembly (PCBA) and a casing, wherein the PCBA is partially housed in the casing, and the PCBA further includes a USB connector protruding out of the casing at a first end of the casing. The piece of string is coupled to the main body and the cap. The cap is detachably coupled to the first end of the casing of the main body to cover the USB connector, wherein the cap remains indirectly coupled to the casing via the piece of string when the cap is detached from the first end of the casing to expose the USB connector.

Abstract: A Universal Serial Bus (USB) flash drive includes a slim USB device having an end used to couple the USB flash drive to a host and an opposite end, and a swivel “strap shaped” metal cap having a circle cut out disposed on both cap legs. The snap coupling circle attachment allows the swivel cap to rotate substantially into a first and a second locking position and to rotate substantially 360 degrees about the z-axis of the USB device. The metal cap is generally in a locked position when the snap slot is aligned atop the snap lock tabs such that the protrusion snap ring is descended downward until the positioned flush against the snap lock groove. When unlocked the protrusion snap ring is raised up and rested upon the two snap lock tabs.

Abstract: A flash-memory device has a printed-circuit board assembly (PCBA) with a PCB with a flash-memory chip and a controller chip. The controller chip includes an input/output interface circuit to an external computer over a Secure-Digital (SD) interface, and a processing unit to read blocks of data from the flash-memory chip. The PCBA is encased inside an upper case and a lower case, with SD contact pads on the PCB that fit through contact openings in the upper case. Supporting end ribs under each of the SD contact pads and middle ribs support the PCB at a slanted angle to the centerline of the device. The PCB slants upward at the far end to allow more thickness for the chips mounted to the bottom surface of the PCB, and slants downward at the insertion end to position the SD contact pads near the centerline.