Abstract: A dynamic gate control signal generator circuit includes a pad configured to produce an output voltage, a reference generator configured to receive a supply voltage (VDDIO) and produce, based on the supply voltage, a first reference voltage signal and a second reference voltage signal, and a pad tracker circuit coupled to the reference generator, the pad tracker circuit configured to receive the output voltage of the pad and limit a high voltage of the pad to the second reference voltage signal. The dynamic gate control signal generator circuit further includes a first clamper circuit coupled to the pad tracker, the first clamper circuit configured to receive an output voltage signal from the pad tracker circuit and generate, based on the output voltage signal, a dynamic gate control signal that toggles between the first reference voltage signal and the second reference voltage signal.

Abstract: A current may be passed through a channel of an anti-fuse field-effect transistor (FET) to increase a temperature of a gate dielectric of the anti-fuse FET and change a rupture voltage of the gate dielectric of the anti-fuse FET from a first rupture voltage to a second rupture voltage. The gate dielectric may be ruptured by applying a first voltage between the gate dielectric and the channel of the anti-fuse FET, where the first voltage is between the first rupture voltage and the second rupture voltage.

Abstract: A first current may be passed through a channel of a fuse field-effect transistor (FET) to heat a gate of the fuse FET. A second current may be passed between a first gate terminal and a second gate terminal of the gate of the fuse FET to permanently degrade one or more electrical characteristics of the fuse FET.

Abstract: In an example, a multi-level data structure is defined including fine grid (FG) and coarse levels. The FG level is configured to store FG data of FG points. The coarse level is configured to store, for a respective chunk of FG points, compressed FG data and/or a pointer to corresponding FG data of the respective chunk. First chunks are identified by a graphics processing unit (GPU) and include each chunk of the FG points including one or more of: (i) that includes a FG point in a level set layer L0 (LSL0), and (ii) that neighbors a chunk that includes the FG point in the LSL0. Memory of the GPU is allocated for the first chunks that have respective compressed FG data to be decompressed. Level set values of the FG points in the LSL0 stored in the FG level in the allocated memory are updated by the GPU.

Abstract: A processing device identifies a first clock tree topology for a circuit design, the first clock tree topology having a threshold feedthrough count and a first timing solution. The processing device further identifies one or more additional clock tree topologies for the circuit design, each of the one or more additional clock tree topologies having a different respective feedthrough count that is less than the threshold feedthrough count, and each of the one or more additional clock tree topologies comprising a respective timing solution. In addition, the processing device receives a selection of at least one of the first clock tree topology or the one or more additional clock tree topologies, and generates the circuit design according to the selection.

Abstract: A method and system are provided for controlling clock operation in a memory that applies a test mode to test functionality of the memory which controls timing in a self-time loop using an external clock that on a rising edge triggers a main clock and on a falling edge provides a reset timer return path to reset the main clock signal. In the reset timer return path, a rising edge of the external clock triggers start of a self-time loop, and the rising edge of the external clock also controls the reset timer return path to block generation of a reference bit line (RBL) signal. In the reset timer return path, a falling edge of the external clock generates the RBL signal to provide an external clock return signal to enable an end of cycle for the self-time loop.

Abstract: An assigning device (100) for assigning fixed identifiers to fuzzy identifiers, the assigning device comprising a database storing multiple fuzzy identifiers, and a matching unit (130) arranged to determine if a matching fuzzy identifier exists in the database that matches a fuzzy input identifier according to a matching criterion and to determine if a matching fuzzy identifier does not exist in the database according to an absent criterion.

Abstract: A block of circuitry contains at least one sub-block. Test patterns for the sub-block (sub-level test patterns) include sub-level test stimuli and corresponding sub-level test responses. These are ported to the block-level to produce block-level test patterns, block-level test stimuli, and block-level test responses. The block-level test patterns are validated as follows. Propagation of the block-level test stimuli through the block-level design is computed. The signals produced by such computed propagation at the sub-block inputs are compared against the sub-level test stimuli, and the signals produced by such computed propagation at the block outputs are compared against the block-level test responses.

Abstract: A computer-implemented method including: providing a test template for a hardware system-under-test comprising one or more execution threads, wherein the test template comprises a branching instruction to a predetermined shared memory address accessible by at least some of the one or more execution threads; generating and storing, at the predetermined shared memory address, a sequence of instructions which conform to the test template; building, based, at least in part, on the test template, an executable image of a hardware exerciser, wherein the hardware exerciser is adapted to control a test cycle of the hardware system-under-test, and wherein the test cycle comprises at least generation and execution of a test; and executing the executable image of the hardware exerciser by at least a first execution thread of the one or more execution threads of the hardware system-under-test.

Abstract: Systems and methods for supporting multiple data rates are presented. A method includes generating a clock signal from a clock source, serializing, by an analog serializer, a data stream in response to the clock signal to output N data in parallel, coupling a pulse generation circuit to the clock signal, wherein a first switch and a second switch electrically communicate with the pulse generation circuit, and coupling a multiplexer to the pulse generation circuit, wherein the multiplexer receives the N data from the analog serializer and selects a subset of the N data when switching operation of the electronic circuit from a first mode to a second mode.

Abstract: Described is a configuration to remove false paths from an emulation netlist in a chip design under test (DUT). The configuration identifies, in an original netlist, an original subgraph of original logic gates, a subset of inputs (TI), and a subset of outputs (TO). The configuration generates a replicated subgraph of the original subgraph, the replicated subgraph having replicated logic gates corresponding to the original logic gates. The configuration connects the TI with a first replicated logic gate to a constant propagation source and remaining inputs of the replicated logic gates with corresponding original logic gates in the original netlist. The configuration disconnects, in the original netlist, output loads of TO, and connects the output loads of TO with a corresponding equivalent TO in the replicated subgraph. The configuration deletes, in the original netlist, original logic gates unconnected with an output load for TO in the original netlist.

Abstract: A memory device includes clock signal generation circuitry, and first integrated level shifter and latch circuitry. The clock signal generation circuitry receives a first clock signal and an isolation signal, and generates a second clock signal based on the first clock signal and the isolation signal. The isolation signal corresponds to a power state of a power supply associated with the first clock signal. The first integrated level shifter and latch circuitry receives an input signal in a first power supply domain, and latches a value the input signal based on the second clock signal. Further, the first integrated level shifter and latch circuitry outputs, based on the latched value, an output signal in a second power supply domain different than the first power supply domain.

Abstract: A memory device includes a memory device and control circuitry. The memory array includes bitcells and bitlines connected to the bitcells. The bitcells are grouped into bitcell groups. The control circuitry is connected to the bitcell groups via the bitlines. The control circuitry adjusts connections with the bitcell groups to include a first bitcell group of the bitcell groups in memory operations and exclude a second bitcell group of the bitcell groups from the memory operations based on a half-word control signal being enabled.

Abstract: Embodiments of the present disclosure relate to a system and method for incremental compilation. The method includes identifying a change to a portion of a circuit design. The circuit design without the change was previously compiled to an FPGA. The method also includes configuring a transactor of the FPGA to simulate the portion of the circuit design with the change and configuring the FPGA to use the transactor to simulate the portion of the circuit design with the change.

Abstract: A system and method for mitigating memory transaction conflicts by receiving a first memory transaction from a first processor slice of a processor and a second memory transaction from a second processor slice of the processor. Further, one or more control signals are generated for the first memory transaction and the second memory transaction based on a determination that the first memory transaction and the second memory transaction have a target address associated with a first memory bank of a memory. The first memory transaction is selected to output to the first memory bank based on the one or more control signals.

Abstract: A check-out request for a license may be received from an application, e.g., an electronic design automation (EDA) application, and may be routed to a license server. The license may be granted to the application, where granting the license to the application may include establishing a connection between the license server and the application. A check-in request may be received for the license from the application. The license may be revoked, which may include terminating the connection between the license server and the application. A usage amount may be determined based on information about the check-out request and information about the check-in request.

Abstract: Merging store instructions for a memory includes receiving a first store instruction having a first address, and determining a first pattern based on a comparison of the first address and a second address of an entry within a buffer. Further, a size field of the entry is updated based on the first pattern. The first address of the first store instruction is merged with the second address within the entry to generate a merged instruction. The merged store instruction is communicated to the memory.

Abstract: A system and method for automated topology recognition and functional annotation of a mixed-signal circuit is disclosed. The method includes extracting structural information available from the mixed-signal circuit. The method includes identifying functionality of a sub-circuit of the mixed-signal circuit based on the extracted structural information by comparing the sub-circuit with a library cell. The method includes annotating the extracted structural information with the identified functionality corresponding to the sub-circuit. The method includes automatically generating a plurality of configurations corresponding to the annotated structural information.

Abstract: A configuration may identify an IC chip component the IC chip component comprising one of a logic block, a memory block, and a power grid. A configuration may train a machine learning model based on one or more features and one or more labels corresponding to the identified IC chip component. A configuration may generate an artificial intelligence model having characteristics comprising the trained machine learning model, the one or more features, and the one or more labels. A configuration may generate a prediction for the one or more labels based on past, present and projected one or more features. A configuration may monitor future label prediction versus a failure threshold. A configuration may generate a notification in response to the failure threshold being reached.

Abstract: A system and method service memory transaction requests by receiving a memory transaction request for a first memory line from a first processor core of processor cores of a processing system. A second processor core of the processor cores is determined to include the first memory line in a shared state. Data of the first memory line is communicated from the second processor core to the first processor core based on determining that the second processor core comprises the first memory line in a shared state.