Patents Assigned to Synopsys, Inc.
  • Patent number: 11514209
    Abstract: Circuitry and processes are disclosed that use conventional electronic circuits (comprising, for example, phase locked loops, pulse width modulators, phase modulators, digital logic gates, etc.) to enable quantum algorithms. Such circuitry and processes achieve the requirement for non-quantum devices to enable quantum algorithms: the tensor product entanglement of signals representing quantum states. Such circuitry and processes are readily usable by current Electronic Design Automation tools, to design, verify and emulate applications such as fast, very large number factoring for use in decryption. Also, the independent Claims concisely signify embodiments of the claimed inventions.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: November 29, 2022
    Assignee: Synopsys, Inc.
    Inventor: Hugo Miguel Fernandes Ramos
  • Patent number: 11507719
    Abstract: A system and method for providing formal property verification across circuit design versions is described. In one embodiment, the system receives a first version and a second version of a circuit design. The received first version has a first set of constraints, a first set of next-state functions representing the first version of the circuit design, and a first property that has been verified as true for the first version of the circuit design. The received second version has a second set of constraints, a second set of next-state functions representing the second version of the circuit design, and a second property for the second version of the circuit design. The described embodiments further construct a composite circuit design based on the first set of constraints, the first set of next-state functions, and the first property and further based on the second set of constraints, the second set of next-state functions, and the second property.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: November 22, 2022
    Assignee: Synopsys, Inc.
    Inventors: Sudipta Kundu, Mitesh Jain
  • Publication number: 20220366120
    Abstract: A method of implementing an automated technology for conducting functional safety (FuSa) diagnostic coverage is provided. The method can include receiving functional safety information that includes failure modes defining wrong values of a signal indicating a factor manifesting an error, receiving an identification of internal safety protected signals and a diagnostic coverage for the FuSa block, performing back tracing of possible paths for an output port of a FuSa block for each failure mode of each safety protected signal, determining an area for each possible path, and determining, based on a diagnostic coverage and area calculated for each of the paths, a diagnostic coverage for each failure mode of the FuSa block.
    Type: Application
    Filed: May 13, 2022
    Publication date: November 17, 2022
    Applicant: Synopsys, Inc.
    Inventors: Mehulkumar Kantibhai GOR, Vishal Ramkrishna SHENVI, Shekhar Sharan BHATIYA
  • Patent number: 11501048
    Abstract: A machine learning model predicts the hardness of unsolved properties. For example, the machine learning model may predict the relative hardness of pairs of properties—i.e., which property in the pair is harder to solve. These hardness predictions may then be used to formulate a priority order for a formal verification process to attempt to solve the unsolved properties. As the formal verification process progresses, it generates results. For example, certain properties may be solved. These results are used to update a training set, which is used to further train the machine learning model. The machine learning model is trained at runtime with incremental fine-tuning as the formal verification process progresses.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: November 15, 2022
    Assignee: Synopsys, Inc.
    Inventors: Arunava Saha, Chuan Jiang, Manish Pandey
  • Patent number: 11501050
    Abstract: A design for an analog mixed-signal (AMS) circuit is accessed. An assertion for verifying the behavior of an analog signal in the AMS circuit is also accessed. The assertion is expressed in an assertion language for AMS circuits. A processor verifies the assertion against the predicted behavior of the analog signal in the AMS circuit. In various embodiments, the assertion language contains predefined classes for assertions in the temporal domain, for assertions in the frequency domain, and for assertions based on functional dependencies of an output analog signal on an input analog signal.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: November 15, 2022
    Assignee: Synopsys, Inc.
    Inventors: Dmitry Korchemny, Eduard R. Cerny, Ilya Kudryavtsev
  • Patent number: 11494539
    Abstract: The design of Dynamic Random Access Memory (DRAM) pass transistors is provided via generating a first plurality of transistor leakage currents by simulating different dopant configurations in a transistor; generating a second plurality of transistor leakage currents by simulating, for each dopant configuration of the different dopant configurations, a single trap insertion in the transistor; fitting the first and second pluralities of transistor leakage currents with first and second leakage current distributions; combining the first and second leakage current distributions to produce a third leakage current distribution; generating a third plurality of statistically generated leakage currents for a specified trap density for the transistor based on the first leakage current distribution, on the second leakage current distribution and on a specified trap density; and modeling and evaluating a DRAM cell including the transistor based on the third plurality of statistically generated leakage currents.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: November 8, 2022
    Assignee: Synopsys, Inc.
    Inventors: Salvatore Maria Amoroso, Plamen A. Asenov, Jaehyun Lee, Andrew R. Brown, Manuel Aldegunde Rodriguez, Binjie Cheng, Andrew John Pender, David T. Reid
  • Patent number: 11491648
    Abstract: A linear motion actuation system and method of using the same may be utilized for installing or removing a server blade within a server rack, via a linear motion assembly fastened to a server blade and configured for linear motion with the server blade; a bracket fastened to a server rack; and at least one linear motion actuator comprising: a first component secured with the linear motion assembly; and a second component movably secured with the first component and secured with the bracket. The second component is configured for at least substantially linear movement relative to first component, and the at least one linear motion actuator is configured to, upon receipt of a signal from a controller, move the second component in an at least substantially linear direction relative to the first component to move the server blade relative to the server rack.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: November 8, 2022
    Assignee: Synopsys, Inc.
    Inventor: Chih I. Wu
  • Patent number: 11494199
    Abstract: A system and method for knob refinement. A method includes determining an ordered list of knobs organized with respect to impact on the target metric for a system based on a plurality of historical sets of target metric measurements; determining a second system configuration based on the ordered list of knobs and a first set of target metric measurements recorded for the system when the system is configured according to a first system configuration, the system having a plurality of knobs, wherein the second system configuration includes at least one knob of the plurality of knobs that is reconfigured as compared to the first system configuration; and applying one of the first system configuration and the second system configuration, wherein the applied system configuration is determined based on the first set of target metric measurements and a second set of target metric measurements.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: November 8, 2022
    Assignee: Synopsys, Inc.
    Inventors: Tomer Morad, Omer Yehezkely, Tomer Paz, Andrey Gelman, Michael Tseitlin
  • Patent number: 11493971
    Abstract: A method of power test analysis for an integrated circuit design including loading test vectors into a first sequence of flip-flops in scan mode, evaluating the test vectors and saving results of the evaluating in a second sequence of flip-flops in scan mode, reading results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vectors are received from an automatic test pattern generator.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: November 8, 2022
    Assignee: Synopsys, Inc.
    Inventors: Alexander John Wakefield, Khader Abdel-Hafez
  • Publication number: 20220350950
    Abstract: A method includes obtaining a target integrated circuit (IC) layout, accessing a repository, identifying a device within the target IC layout by matching an area of the target IC layout to a source pattern, and replacing at least a portion of the area of the target IC layout with a replacement pattern. The repository stores the source pattern for the device and the replacement pattern corresponding to the source pattern.
    Type: Application
    Filed: May 2, 2022
    Publication date: November 3, 2022
    Applicant: Synopsys, Inc.
    Inventors: Soo Han CHOI, Anil KARANAM, Elango VELAYUTHAM, Yuli XUE
  • Patent number: 11487930
    Abstract: Pattern matching using anchors during integrated circuit (IC) verification is disclosed. According to one embodiment, a method includes obtaining match time estimates associated with pattern anchors of different anchor types for an IC pattern, generating revised match time estimates based on a target IC layout, and then selecting the pattern anchor associated with the shortest revised match time estimate. Then, target anchors of the same anchor type as the selected pattern anchor are generated for the target IC layout, and the target IC layout is searched for the IC pattern using the selected pattern anchor and the target anchors.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: November 1, 2022
    Assignee: Synopsys, Inc.
    Inventors: Chen Gao, Yuli Xue, Tony Tan, Weiping Fang
  • Patent number: 11489102
    Abstract: Josephson junction (JJ) structures are disclosed. In some embodiments, a JJ structure may include a first superconducting structure and a second superconducting structure disposed on a plane parallel to a silicon wafer surface. A non-superconducting structure may be disposed between the first superconducting structure and the second superconducting structure. A direction of current flow through the non-superconducting structure may be parallel to the silicon wafer surface.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: November 1, 2022
    Assignee: Synopsys, Inc.
    Inventors: Jamil Kawa, Victor Moroz, Stephen Robert Whiteley
  • Patent number: 11475201
    Abstract: A method of generating a mask used in fabrication of a semiconductor device includes, in part, selecting a source candidate, generating a process simulation model that includes a stochastic variance band model in response to the selected source candidate, performing a first optical proximity correction (OPC) on the data associated with the mask in response to the process simulation model, assessing one or more lithographic evaluation metrics in response to the OPC mask data, computing a cost in response to the assessed one or more lithographic evaluation metrics, and determining whether the computed cost satisfies a threshold condition. In response to the determination that the computed cost does not satisfy the threshold condition, a different source candidate may be selected.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: October 18, 2022
    Assignee: Synopsys, Inc.
    Inventors: William Stanton, Sylvain Berthiaume, Lawrence S. Melvin, III, Ulrich Klostermann
  • Patent number: 11475293
    Abstract: A method of estimating a toggle count of a circuit, includes, in part, simulating the circuit to generate training data and an associated training toggle count of the internal nodes of the circuit in response to a test bench, training a neural network system to generate an estimate of the training toggle count in accordance with the training data and the associated training toggle count, simulating the circuit to generate simulation data in response to a first set of input values applied to the circuit, and invoking the trained neural network system to estimate a number of toggles of the internal nodes of the circuit from the simulation data. The training data may include, in part, values of input signals applied to the circuit and values of registers disposed in the circuit for a multitude of time stamps. The neural network system may include, in part, at least three layers.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: October 18, 2022
    Assignee: Synopsys, Inc.
    Inventors: Gung-Yu Pan, Chia-Chih Yen, Che-Hua Shih
  • Patent number: 11475197
    Abstract: A circuit hardware emulation module is configured to identify oscillating subgraphs of an emulated graph, or to identify state-holding subgraphs of an emulated graph. The emulation module identifies one or more loops within an emulated circuit; generates an acyclic emulation of at least a portion of the emulated circuit, wherein the acyclic emulation is characterized by one or more loop breakers; generates a loop detector emulation of a hardware-based loop detector circuit based at least in part on a quantity of loop breakers n characterizing the acyclic emulation, wherein the loop detector emulation comprises at least one of an oscillation detector or a state-holding detector; and executes the loop detector emulation for a plurality of input values for the emulated circuit to generate an output indicating at least one of an oscillation status or a state-holding status of the emulated circuit.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: October 18, 2022
    Assignee: Synopsys, Inc.
    Inventors: Olivier Coudert, Florent Duru, Francois Peneloux
  • Publication number: 20220327266
    Abstract: A word-level design model may be loaded into memory. Next, a masking layer may be created which includes objects in the word-level design model that are not used by an IC design analysis system. The masking layer may then be used to provide a reduced block model view on-the-fly to the IC design analysis system.
    Type: Application
    Filed: March 23, 2022
    Publication date: October 13, 2022
    Applicant: Synopsys, Inc.
    Inventors: Mahantesh D. Narwade, Soumen Ghosh, Mark Roizman, Vijaya V. Varkey, Abhinav Singla, Rajarshi Mukherjee
  • Publication number: 20220327272
    Abstract: A method, a system, and a non-transitory computer readable medium for simulating a circuit are provided. The method includes generating a digital simulation file for the circuit that includes a block, generating a mixed simulation file for the circuit, generating a waveform file by executing the digital simulation file for a first time window of a simulation, determining a plurality of analog values for the block based on the waveform file, and executing, by a processor, the mixed simulation file for a second time window of the simulation with the plurality of analog values annotated to the block at a start of the second time window. The digital simulation file corresponds to the block in a digital view and the mixed simulation file corresponds to the block in an analog view.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 13, 2022
    Applicant: Synopsys, Inc
    Inventors: Henry JYU, Xiaonan SHI, Tingting JIANG
  • Patent number: 11467851
    Abstract: Disclosed herein are system, computer-readable storage medium, and method embodiments of machine-learning (ML)-based static verification for derived hardware-design elements. A system including at least one processor may be configured to extract a feature set from a hardware description and evaluate a similarity index of a first hardware element with respect to a second hardware element, using an ML process based on the feature set, wherein the first hardware element is described in the hardware description. The at least one processor may be further configured to update one or more parameters corresponding to a static verification of the hardware description while the static verification is being performed, by providing at least one test attribute, corresponding to the second hardware element, applicable to the first hardware element, in response to determining that the similarity index is within a specified range, and additionally output a first result of the static verification.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: October 11, 2022
    Assignee: SYNOPSYS, INC.
    Inventors: Kaushik De, Rajarshi Mukherjee, Paras Mal Jain, David L. Allen
  • Patent number: 11468222
    Abstract: A method, includes, in part, defining a continuous signal, defining a threshold value, calibrating the continuous signal and the threshold value from measurements made on edges of one or more patterns on a mask and corresponding edges of the patterns on a wafer, convolving the continuous signal with a kernel to form a corrected signal, and establishing, by a processor, a probability of forming an edge at a point along the corrected signal in accordance with a difference between the value of the corrected signal at the point and the calibrated threshold value. The kernel is calibrated using the same measurements made on the patterns' edges.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: October 11, 2022
    Assignee: Synopsys, Inc.
    Inventors: Yudhishthir Prasad Kandel, Lawrence S. Melvin, III
  • Patent number: 11468218
    Abstract: Computer-implemented techniques are disclosed for verifying circuit designs using subgraph caching. A device under test (DUT) is modeled as a graph. The graph is partitioned into one or more subgraphs and problems are generated for each subgraph. Graph and subgraph problem generation is repeated numerous times throughout the verification process. Problems and sub-problems are generated and solved. When a subgraph problem is solved, the problem's variables, values, and information can be stored in a cache. The storage can be based on entropy of variables used in the graph and subgraph problems. The subgraph problem storage cache can be searched for previously stored problems which match another problem in need of a solution. By retrieving subproblem variables, values, and information from the cache, the computational overhead of circuit design verification is reduced as problems are reused. Caching can be accomplished using an information theoretic approach.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: October 11, 2022
    Assignee: Synopsys, Inc.
    Inventors: Dhiraj Goswami, Ngai Ngai William Hung