Patents Assigned to Synopsys, Inc.
  • Patent number: 11176293
    Abstract: The independent claims of this patent signify a concise description of embodiments. A method is provided for reducing a size of an emulation clock tree for a circuit design. The method comprises identifying a fan-in cone of an input of a sequential element of the circuit design; identifying one or more fan-in cone sequential elements which do not directly affect the input of the sequential element; and removing the one or more identified fan-in cone sequential elements of the fan-in cone from the emulation clock tree. This Abstract is not intended to limit the scope of the claims.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: November 16, 2021
    Assignee: Synopsys, Inc.
    Inventors: Dmitry Korchemny, Alexander Rabinovitch, Boris Gommershtadt, Daniel Geist, Srivatsan Raghavan
  • Patent number: 11177317
    Abstract: Integrated circuit devices which include a thermoelectric generator which recycles heat generated by operation of an integrated circuit, into electrical energy that is then used to help support the power requirements of that integrated circuit. Roughly described, the device includes an integrated circuit die having an integrated circuit thereon, the integrated circuit having power supply terminals for connection to a primary power source, and a thermoelectric generator structure disposed in sufficient thermal communication with the integrated circuit die so as to derive, from heat generated by the die, a voltage difference across first and second terminals of the thermoelectric generator structure. A powering structure is arranged to help power the integrated circuit, from the voltage difference across the first and second terminals of the thermoelectric generator. The thermoelectric generator can include IC packaging material that is made from thermoelectric semiconductor materials.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: November 16, 2021
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Jamil Kawa
  • Patent number: 11176306
    Abstract: A method, a system, and non-transitory computer readable medium for level package routing are provided. The method includes performing triangulation on a set of nets to generate a routing resource graph. The objects of the set of nets are represented by a respective center point during triangulation. The method also includes generating a route between the objects of the set of nets based on at least a total cost. The total cost is determined based on at least the routing resource graph. The method also includes altering the route based on a determination that a constraint rule is unmet and outputting routing information comprising the route for the set of nets.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: November 16, 2021
    Assignee: Synopsys, Inc.
    Inventors: About Liao, Bing Chen, Happy Wang, Pagan Chou, Cheng-chieh Chen, Philippe Aubert McComber, Siarhei Lekhtsikau
  • Publication number: 20210350058
    Abstract: A method, apparatus, and/or computer program product can performing an analog defect simulation on an electronic device. The method, apparatus, and/or computer program product can generate a defect catalog which identifies a defect class relating to a defect and a modeling parameter that is associated with the defect class. The method, apparatus, and/or computer program product can receive a weight formula that identifies a weight for the defect class in relation to the modeling parameter. The method, apparatus, and/or computer program product can call a defect weight function to return the weight from the defect weight formula. The method, apparatus, and/or computer program product can perform the analog defect simulation on the electronic device. The method, apparatus, and/or computer program product can determine a simulation statistic relating to the analog defect simulation utilizing the weight.
    Type: Application
    Filed: May 11, 2020
    Publication date: November 11, 2021
    Applicant: Synopsys, Inc.
    Inventors: Mayukh BHATTACHARYA, Miroslava TZAKOVA, Chih-Ping Antony FAN
  • Publication number: 20210350053
    Abstract: The technology disclosed relates to verifying metastability for a clock domain crossing (CDC) in a circuit design. The technology disclosed may include, for a destination clock domain in the circuit design, creating a circuit graph based, at least in part, on the circuit design. The circuit graph includes start points and stop points. The start points may be data inputs, clocks, and enables of the destination clock domain. The stop points may be synchronizer outputs of the destination clock domain and a source clock domain in the circuit design. The technology disclosed may also include traversing the circuit graph to mark all graph nodes that reside in a source-destination path of the CDC. Based on the marked graph nodes, the start points, and the stop points, the technology disclosed may also include propagating destination domain qualifiers on the circuit graph within an allowed sequential depth.
    Type: Application
    Filed: May 10, 2021
    Publication date: November 11, 2021
    Applicant: Synopsys, Inc.
    Inventors: Deepak AHUJA, Anchit JAIN, Paras Mal JAIN
  • Publication number: 20210349845
    Abstract: A method including creating a first bus guide and a second bus guide of a plurality of bus guides for an integrated circuit is disclosed. The method includes routing the first bus guide and the second bus guide through a plurality of layout blocks of the integrated circuit. The method includes annotating the first bus guide or the second bus guide to identify a plurality of areas for placing a plurality of repeaters within the first bus guide or the second bus guide. The method includes, based on the annotated first bus guide and the second bus guide, generating, by at least one processor, a plurality of guidance directories corresponding to a plurality of routes through the plurality of layout blocks for placing the plurality of repeaters at the plurality of layout blocks on the identified plurality of areas on the first bus guide or the second bus guide.
    Type: Application
    Filed: May 7, 2021
    Publication date: November 11, 2021
    Applicant: Synopsys, Inc.
    Inventors: Kai-Ping WANG, Songmei CHEN, Ying LIU, Xiaolin YUAN
  • Patent number: 11171460
    Abstract: A tool for coupling and decoupling a connector of a cable. The tool includes a body, a bracket, and a first hook. The body has a first end portion, a second end portion opposite the first end portion, and an intermediate portion between the first end portion and the second end portion. The body has a longitudinal axis running between the first end portion and second end portion. The body also has a first surface and a second surface opposite the first surface. The bracket is disposed at the first end portion. The bracket defines a cavity configured to receive a portion of the connector, and the bracket is configured to push the connector as the tool moves in a first direction. The first hook is disposed at the intermediate portion. The first hook is configured to engage an opening defined by the connector and pull the connector as the tool moves in a second direction different than the first direction.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: November 9, 2021
    Assignee: Synopsys, Inc.
    Inventor: Chih I Wu
  • Patent number: 11164624
    Abstract: A system to enable detection of the process corner of each of the P and N devices of an SRAM array (of bitcells) and of peripheral devices. This permits more focused (optimized and compensated) design of non-SRAM peripheral circuits and of read and write assist circuits for better handling of process distribution impact on circuits improving functionality and yield.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: November 2, 2021
    Assignee: Synopsys, inc.
    Inventors: Tzong-Kwang Henry Yeh, Jamil Kawa
  • Publication number: 20210333853
    Abstract: A method of power test analysis for an integrated circuit design including loading test vectors into a first sequence of flip-flops in scan mode, evaluating the test vectors and saving results of the evaluating in a second sequence of flip-flops in scan mode, reading results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vectors are received from an automatic test pattern generator.
    Type: Application
    Filed: April 26, 2021
    Publication date: October 28, 2021
    Applicant: Synopsys, Inc.
    Inventors: Alexander John Wakefield, Khader Abdel-Hafez
  • Patent number: 11159163
    Abstract: A circuit includes three PMOS transistors (PMOS) and three NMOS transistors (NMOS). The first PMOS has a source receiving a supply voltage and a gate receiving a first signal. The second PMOS has a source coupled to a drain of the first PMOS, a gate receiving a clock signal, and a drain generating a second signal. The third PMOS has a source receiving the supply voltage, and a drain coupled to the drain of the second PMOS. The first NMOS has a drain coupled to the drain of the second PMOS, and a gate coupled to a gate of the third PMOS. The second NMOS has a gate receiving the first signal, and a drain coupled to a source of the first NMOS. The third NMOS has a gate coupled to the gate of the third PMOS transistor, and a drain coupled to the drain of the third PMOS.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: October 26, 2021
    Assignee: Synopsys, Inc.
    Inventors: Pradip Subhana Jadhav, John Pasternak
  • Publication number: 20210326227
    Abstract: A system and method of detecting defects in an analog circuit is provided. A method includes identifying a channel connected block (CCB) from a netlist, creating defect for the CCB to be injected during a simulation, obtaining a first measurement of an output node of the CCB by performing a first analog circuit simulation for the CCB based on providing excitations as inputs to the CCB and obtaining a second measurement of the output node of the CCB by performing a second analog circuit simulation for the CCB based on providing the excitations as the inputs to the CCB and injecting the defect. The method can further include determining a defect type based on the first measurement and the second measurement.
    Type: Application
    Filed: April 15, 2021
    Publication date: October 21, 2021
    Applicant: Synopsys, Inc.
    Inventors: Mayukh Bhattacharya, Huiping Huang, Antony Fan
  • Patent number: 11152313
    Abstract: The independent claims of this patent signify a concise description of embodiments. Roughly described, a physically unclonable function (PUF) device includes a crystalline substrate and a stack of crystalline layers on top. The stack is grown epitaxially such that lattice mismatch causes threading dislocations from the substrate to the top surface of the stack. Diodes are formed on the top surface by forming anode material on the top surface of the stack, thereby forming a diode junction with a cathode region below. A diode which includes a threading dislocation has a higher leakage current than one that does not. Circuitry connected to the diodes interrogates the array and outputs binary values indicating, for each of the diodes, whether the diode includes a threading dislocation. Such binary values can be used as the PUF of the chip. This Abstract is not intended to limit the scope of the claims.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: October 19, 2021
    Assignee: Synopsys, Inc.
    Inventors: Hiu Yung Wong, Rimvydas Mickevicius
  • Patent number: 11151294
    Abstract: One or more embodiments disclosed herein pertain to a hybrid emulation system for hybrid emulation of a design under test (DUT). The system comprises a hardware emulation system to emulate a first portion of the DUT during the hybrid emulation. The hardware emulation system includes emulated registers for the first portion of the DUT. The hybrid emulation system also comprises a simulation system to simulate a second portion of the DUT during the hybrid emulation. The hybrid emulation system additionally comprises a configuration file that identifies a subset of the emulated registers. The simulation system is configured with the configuration file to selectively mirror, during the hybrid emulation, the subset of the emulated registers identified by the configuration file.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: October 19, 2021
    Assignee: Synopsys, Inc.
    Inventors: Andreas Gerd Ropers, Sylvain Bayon de Noyer, Alexandru Fiodorov, Filip Constant Thoen, Markus Wedler
  • Patent number: 11144690
    Abstract: Techniques and systems for implementing a general extensible layer mapping approach that maps between integrated circuit (IC) design database layers and process layers are described. A first IC design layout having in-design layers can be converted into a second IC design layout having derived layers, wherein said converting comprises mapping the in-design layers to the derived layers by applying a set of layer derivation rules to shapes in the IC design layout, and wherein the set of layer derivation rules implements a one-to-many mapping between the in-design layers and the derived layers. Next, a one-to-one mapping between the derived layers and process layers used in a parasitic extraction tool can be generated. Parasitic extraction on the IC design layout then be performed by providing the second IC design layout and the one-to-one mapping to the parasitic extraction tool.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: October 12, 2021
    Assignee: Synopsys, Inc.
    Inventors: Jun Wang, Yun-Jui Li, Bin Xu, Cheng-Ming Wu, Yu Fan Lu, Hu Cai, Yuting Fu, Hwei-Tseng Wang, Sui Zheng, Jeong-Tyng Li
  • Patent number: 11144700
    Abstract: Route segments of a set of nets may be grouped into route groups. Terminals of the set of nets may be grouped into terminal groups. For each net in the set of nets, a net signature may be determined based on route groups associated with the net and terminal groups associated with the net. The set of nets may be grouped into net groups based on the net signatures.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: October 12, 2021
    Assignee: Synopsys, Inc.
    Inventors: Kai-Ping Wang, Iris E. Chen
  • Patent number: 11145344
    Abstract: A method includes performing a first read operation on a memory cell of a programmed first one-time programmable (OTP) anti-fuse to determine a state of the memory cell based on a first parameter level, performing a second read operation on the memory cell of the programmed first OTP anti-fuse to determine the state of the memory cell based on a second parameter level, identifying the memory cell of the first OTP anti-fuse as an uncertain bit when the state determined during the first read operation and the state determined during the second read operation are different, and programing one or more memory cells of a second OTP anti-fuse based on a bit position of the identified uncertain bit of the first OTP anti-fuse.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: October 12, 2021
    Assignee: Synopsys, Inc.
    Inventor: Xiaojun Lu
  • Patent number: 11144703
    Abstract: A computerized system is disclosed. The computerized system may include one or more processors configured to perform the operations stored in a memory. The operations may include creating a plurality of library (lib) cells for a directional routing layer, and determining a lib cell of the plurality of lib cells for placement of at least one repeater for the directional routing layer. The operations may also include determining a route touch region corresponding to a pin region of the lib cell through which a route is going through and inserting the at least one repeater at the route touch region. The operations may also include swapping the at least one inserted repeater to at least one target lib cell of the plurality of lib cells.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: October 12, 2021
    Assignee: Synopsys, Inc.
    Inventors: Kai-Ping Wang, Haiying Liu
  • Publication number: 20210312113
    Abstract: In modern VLSI technology, often, stacked arrays of smaller sized MOSFETs are used to achieve the desired width and length of a design MOSFET. In analog defect simulation, each physical transistor can contribute to the circuit's defect universe and this can directly lead to tremendous increase in defect simulation time. Here we propose a method of finding equivalent defects in the context of stacked MOSFET arrays that can lead to significant reduction in defect simulation effort and yet provide accurate defect coverage results.
    Type: Application
    Filed: April 2, 2021
    Publication date: October 7, 2021
    Applicant: Synopsys, Inc.
    Inventors: Mayukh BHATTACHARYA, Michal Jerzy Rewienski, Shan Yuan, Michael Durr, Chih Ping Antony Fan
  • Patent number: 11139402
    Abstract: The independent claims of this patent signify a concise description of embodiments. Disclosed is technology, roughly described, in which a semiconductor structure includes a substrate supporting a column of at least one (and preferably more than one) horizontally-oriented nanosheet transistor, each having a respective channel segment of semiconductor crystalline nanosheet material (preferably silicon or a silicon alloy) sheathed by gate stack material, wherein the channel segments have a diamond cubic crystal structure and are oriented such that the {111} planes are horizontal. Also disclosed is a method for fabricating such a structure, and a corrugated substrate that may be formed as an intermediate product. This Abstract is not intended to limit the scope of the claims.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: October 5, 2021
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Ignacio Martin-Bragado
  • Patent number: 11138356
    Abstract: A power usage estimation system for a design emulated on a field programmable gate array (FPGA) comprising a periodic dump unit implementing statistical data sampling to generate a periodic dump without emulation stops and interactions with a host, and without affecting the emulation performance.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: October 5, 2021
    Assignee: Synopsys, inc.
    Inventors: Alex Potapov, Boris Gommershtadt, Yan Zucker