Abstract: A first voltage value is determined using a comparator operating based on a first hysteresis value. A second voltage value is determined using the comparator operating based on a second hysteresis value and in dependence on the first voltage value. One or more indications of at least one of the first voltage value and the second voltage value are provided.

Abstract: A system and method for temporal control of fault functional verification. In some embodiments, a method includes: determining, in a nominal functional verification of a circuit, that an output of a first component has a first value at a first point in time, the output of the first component being connected to an input of a second component by a wire; determining, in a fault functional verification of the circuit, that the output of the first component has a second value, different from the first value, at the first point in time; determining, based on runtime input, that the wire passes through a barrier; and setting, in the fault functional verification, the value of the input of the second component, at the first point in time, to the first value.

Abstract: A method includes accessing, by a processing device, an electronic design of an integrated circuit. The method further includes generating a virtual block corresponding to an actual block of the electronic design, the virtual block including a plurality of virtual subblocks corresponding to a plurality of actual subblocks in the actual block. The method also includes cloning or shallow copying contents of the plurality of actual subblocks in the corresponding virtual subblocks, wherein the cloned contents in the virtual subblocks are linked to the corresponding actual subblocks and no data is copied.

Abstract: An apparatus may include an amplifier loop to generate a first bias voltage, and a first outer ballast stage having a first transistor chain, where an output of the amplifier loop is connected to a first gate of a first transistor of the first outer ballast stage, and a second gate of a second transistor of the first outer ballast stage is connected to a first control signal to enable and disable the first outer ballast stage. The apparatus may further include a second outer ballast stage having a second transistor chain, where a bias current on a reference voltage output rail driven by at least the first and second outer ballast stages is based upon a number of outer ballast stages that are enabled.

Abstract: Techniques for improved analysis and simulation of an IC design are disclosed. Simulation activity for an integrated circuit (IC) design is identified using one or more processors. One or more potential improvements to a simulation of the IC design are generated based on the simulation activity, the one or more potential improvements relating to at least one of signal activity or process activity, during simulation, reflected in the simulation activity. A hardware description language (HDL) design file corresponding to the IC design is modified to indicate the one or more potential improvements to the simulation.

Abstract: A method includes accessing, by a processing device, an electronic design of an integrated circuit. The method further includes generating a virtual block corresponding to an actual block of the electronic design, the virtual block including a plurality of virtual subblocks corresponding to a plurality of actual subblocks in the actual block. The method also includes cloning or shallow copying contents of the plurality of actual subblocks in the corresponding virtual subblocks, wherein the cloned contents in the virtual subblocks are linked to the corresponding actual subblocks and no data is copied.

Abstract: A system and method for determining the location of safety mechanisms to be placed within a circuit design by receiving a circuit design and a safety relevant input. A first cone a first cone of influence and a first apex point of the first cone of influence are determined based on the safety relevant input. The first cone of influence includes first circuit elements of the circuit design. A location of a first safety mechanism to be placed within the circuit design is determined based on the first cone of influence and the first apex point.

Abstract: Optimizing ML models for resource constraints in electronic design automation (EDA) computer aided design (CAD) flows, including computing a set of bin thresholds based on slope changes in an ordered set of discrete probabilistic classification scores, assigning the discrete probabilistic classification scores to the bins based on the values of the discrete probabilistic classification scores and the bin thresholds, and selecting processes associated with the discrete probabilistic classification scores of one or more of the bins based on costs of the respective processes and a global budget.

Abstract: A memory device may include a first cell and a second cell, where the first cell and the second cell are each to store at least a first data bit value. The memory device may further include at least one noise protection device linking the first cell and the second cell that is configured to dissipate at least a portion of noise originating in one of: the first cell or the second cell to another of: the first cell or the second cell.

Abstract: A system includes: an error correction code (ECC) memory controller configured to read data stored in a memory, the data including a read codeword including system data and parity data, the ECC memory controller including an ECC decoder configured to: compute a syndrome based on the read codeword using a parity-check matrix including a plurality of columns, wherein a first group of syndromes calculated by the parity-check matrix in a case where the read codeword has a double-bit error and a virtually stored known bad data bit is set and a second group of syndromes calculated by the parity-check matrix in a case where the read codeword has a single-bit error or zero errors are disjoint; and in a case where the read codeword received has a double bit error and a virtually stored known bad data bit, detect an error and output an indication of detection of the error.

Abstract: A system and method predicts performance of a circuit design by receiving circuit design training data and circuit design test data. The circuit design training data includes training nodes and training paths. The training paths connect the training nodes including circuit components. The circuit design test data includes a first test node and a second test node. Further, testing information is determined for the circuit components of each training path from the circuit design training data. A statistical representation of the circuit design test data is determined based on the testing information and the circuit design test data, and first test information for a test path connecting the first test node with the second test node is determined based on the statistical representation.

Abstract: A level shifter implemented with contention mitigation is disclosed. The level shifter generally includes: an input transistor pair; a first cascode transistor pair coupled in cascode with the input transistor pair, respectively; first cross-coupled transistors; a second cascode transistor pair coupled in cascode with the first cross-coupled transistors, respectively; a first level shifter transistor pair having gates coupled to drains of the second cascode transistors pair, respectively; and a first contention mitigation transistor pair coupled between a first reference voltage node and the first level shifter transistor pair, respectively.

Abstract: A plurality of design iterations are executed for a flow to design a circuit. The design flow includes a sequence of at least two stages. Each stage produces an output design of the circuit from an input design of the circuit, in accordance with parameters for that stage. The design iterations select parameter values for slices of one or more stages of the design flow. In the design iterations for at least one of the slices, parameter values for a non-final stage of the design flow are selected based on a final quality of result (QoR) of the design flow. The design iterations for this slice are adapted based on final QoRs produced by the design iterations.

Abstract: Failsafe IO circuitry is provided that can operate in a failsafe mode and a normal mode. The failsafe IO circuitry can include input circuitry that (i) receives a pad signal (PAD) from driver circuitry, (ii) receives control signals (VDDIO, VREFN) and (iii) provides an output signal (PADBY2) generated based on the received control signals (VDDIO, VREFN), wherein, when operating in a normal mode, the pad signal (PAD) is a floating signal and the output signal (PADBY2) is 0 volts (0V), and power gated logic circuitry that (i) receives the output signal (PADBY2) from the input circuitry, (ii) receives the control signals (VDDIO, VREFN) and (iii) outputs a reference pad failsafe signal (PAD_FS), wherein, when operating in the normal mode, the reference pad failsafe signal (PAD_FS) is 0V.

Abstract: The present disclosure describes systems and methods for generating timing libraries. The apparatus includes a memory and a processor. The processor determines a condition that indicates whether a superconducting electronic circuit design passes or fails logic verification and determines an edge-of-failure value for a timing parameter for the superconducting electronic circuit design. The processor simulates the superconducting electronic circuit design using the edge-of-failure value for the timing parameter and a first process variation to produce a first timing value for the superconducting electronic circuit design and simulates the superconducting electronic circuit design using the edge-of-failure value for the timing parameter and a second process variation to produce a second timing value for the superconducting electronic circuit design.

Abstract: An N-bit successive SAR includes, in part, a differential comparator receiving a pair of differential input signals and generating a pair of differential comparator output signals; an N-bit register storing the comparator output signals; a capacitive DAC supplying differential feedback signals to the differential comparator in response to the register; and M detection circuits each associated with one of M most significant bits of the N-bit register. Each detection circuit includes: a PMOS transistor precharging a first node to a supply voltage; a first NMOS transistor having a drain coupled to the first node, and a gate receiving a first voltage representative of one of the differential feedback signals; a second NMOS transistor having a drain coupled to a source of the first NMOS transistor, a gate receiving a second voltage representative of the other one of the differential feedback signals, and a source coupled to a ground terminal.

Abstract: A circuit includes, in part, a transconductance amplifier, a common source amplifier, a resistor, and NMOS transistor. The common source amplifier is coupled to an output of the transconductance amplifier and generates a signal coupled to an output terminal of a crystal oscillator circuit. The resistor is coupled between the transconductance amplifier and the ground terminal. The NMOS transistor has a drain terminal coupled to a first terminal of the first resistor, a source terminal coupled to a second terminal of the first resistor, and a gate terminal coupled to an input terminal of the common source amplifier and to an input terminal of the crystal oscillator circuit.

Abstract: A method of performing elliptic curve cryptography includes, in part, receiving a scalar k representative of a secret key; and splitting, by a processing device, a multiplication of k by a generator point P on the elliptic curve ([k]P) into a sum of a first multiplication defined by [k?r]P, and a second multiplication defined by [r/n](nP), where n is a power of 2 of an integer number, and r is an integer smaller than k/(2*n); i.e., r<k(/2*n).

Abstract: A method includes: receiving an input job associated with a license type; receiving a license server order including a plurality of license servers; reading license server information regarding the plurality of license servers from a license server information cache; updating, by a processing device, the license server order based on the license server information to compute an updated license server order; and accessing at least one of the plurality of license servers in the updated license server order to attempt license checkout of a license from one of the plurality of license servers, the license being appropriate for the license type of the input job.

Abstract: A method, a system, and a non-transitory computer readable medium for simulating a circuit are provided. The method includes generating a digital simulation file for the circuit that includes a block, generating a mixed simulation file for the circuit, generating a waveform file by executing the digital simulation file for a first time window of a simulation, determining a plurality of analog values for the block based on the waveform file, and executing, by a processor, the mixed simulation file for a second time window of the simulation with the plurality of analog values annotated to the block at a start of the second time window. The digital simulation file corresponds to the block in a digital view and the mixed simulation file corresponds to the block in an analog view.