Abstract: A system generates a mask for a circuit design while enforcing symmetry and consistency across random areas of the mask. The system builds a mask solutions database mapping circuit patterns to mask patterns. The system uses the mask solutions database to replace circuit patterns of the circuit design with mask patterns. The system identifies properties in circuit patterns of the circuit design and enforces the same property in the corresponding mask patterns. Examples of properties enforced include symmetry within circuit patterns and similarity across circuit patterns. The system combines mask patterns in different regions of the circuit and resolves conflicts that occur when there are multiple masks within a region.

Abstract: In some aspects, a mask shape is represented by vertices that are connected by segments. A correction to the mask shape is received. The correction may include displacements of the segments and displacements of the vertices. The mask shape is modified by a processor, as follows. The segments are moved according to the segment displacements. As part of this process, vertices that are endpoints of the moved segments are replicated. The replicated vertices are then collapsed. The resulting vertices are then moved according to the vertex displacements. This process of modifying the mask shape may be used as part of a mask synthesis process, to synthesize or correct the mask shapes according to some desired result.

Abstract: A system performs verification of Ethernet hardware. A data frame including a first portion for storing a checksum value and a second portion for storing a timestamp value is received. The second portion of data frame is set to zero. A timestamp value for including in second portion of the data frame is received. A modified checksum value is determined based on the checksum value included in the first portion of the data frame and the timestamp value. A cyclic redundancy check (CRC) value is determined for the data frame by nullifying the checksum value in the data frame and considering the timestamp value. A final CRC value is determined by combining the CRC value for the data frame and a CRC correction value based on the checksum. The modified data frame is sent for processing using an emulator.

Abstract: Embodiments provide for interactive routing transistor devices of an integrated circuit (IC) design using an interactive routing tool. An example method includes receiving an integrated circuit (IC) design comprising a plurality of transistor devices. The example method further includes receiving a design rule check (DRC) rules set. The example method further includes, responsive to identifying, based at least in part on the DRC rules set, that a first connection input associated with a transistor device of the plurality of transistor devices creates a design rule violation, determining whether a force mode input has been received. The example method further includes, responsive to determining that the force mode input has been received, enabling routing of the first connection input.

Abstract: A method of pruning nets in a circuit design includes, in part, receiving data representative of net layers associated with the circuit design, and accessing a connect database associated with the circuit design. The connect database includes data representative of electrical connections associated with the circuit design. The method further includes, in part, determining whether a marker layer exists in the net layers, and pruning nets that are not connected to the marker layer if the marker layer is determined to exist. The marker layer, which is not stored in the connect database, designates a connection between at least a pair of nets in the circuit design.

Abstract: A system and method that measures the code non-linearity of a phase mixer (PMIX) during active operation of a clock and data recovery (CDR) circuitry. The PMIX circuitry generates a clock signal based on the PMIX codes. The PMIX circuitry receives a plurality of codes and based on the code value, adjusts the phase of the PMIX output clock signal. A number of times each of the plurality of PMIX codes occurs within a respective time period is determined. Non-linearity values are determined based on the number of times. The non-linearity values are stored in a memory.

Abstract: A parameterized superconducting circuit may include a set of sub-blocks which include superconducting circuitry. Different sub-blocks in the set of sub-blocks may be clocked using clock signals having different phases. Along a first direction, relative locations of the set of sub-blocks may be fixed. Along a second direction, relative locations of the set of sub-blocks may be determined based on a set of parameter values.

Abstract: Disclosed herein are a method, a system, and a computer-readable storage-medium embodiments of automatic elastic CPU for a physical verification job. An embodiment includes generating multiple commands for a physical verification job of a design. The multiple commands are related by a dependency graph. The embodiment further includes allocating an initial amount of computing resources to execute the multiple commands, queuing a subset of the multiple commands for execution based on the dependency graph, adding an estimated amount of computing resources to the initial amount based on the number of the queued subset of commands and an estimated time to complete the queued subset of commands, and releasing a portion of the estimated amount of computing resources in response to the portion of the estimated amount of computing resources being idle for an amount of time greater than a target time.

Abstract: A method is disclosed. The method includes computing a time delay for each path of a plurality of paths of a circuit design and determining a commonality score based on a number of segments that are common between the plurality of paths of the circuit design. The method further includes determining a criticality score based on the time delay for each path of the plurality of paths of the circuit design. The method further includes generating a graphical representation of the plurality of paths, wherein a first dimension of the graphical representation corresponds to the commonality score and wherein a second dimension of the graphical representation corresponds to the criticality score. The method further includes providing the graphical representation of the plurality of paths in a graphical user interface (GUI) to represent the plurality of paths in the circuit design.

Abstract: A method for modelling timing behavior using augmented sensitivity data for physical parameters is disclosed. The method includes acquiring timing library data and sensitivity data for a physical parameter associated with a circuit design, generating a timing behavior model for the circuit design based on the timing library data and sensitivity data for the physical parameter, and storing the timing behavior model. The timing behavior model reduces a difference between a current known best measurement associated with the circuit design and a static timing analysis timing for the circuit design.

Abstract: A system and method which compensates for phase mixer circuit non-linearities within a clock and data recovery (CDR) system during active operation. The CDR system includes compensation circuitry and phase accumulation circuitry. The compensation circuitry generates a first compensation signal based on a first compensation value. The phase accumulation circuitry receives the first compensation signal and a phase accumulator input update signal. The phase accumulation circuitry combines the first compensation signal with the phase accumulator input update signal to compensate for a first non-linearity within phase mixer (PMI) circuitry.

Abstract: New techniques for the partitioning of big element blocks in a circuit are disclosed. The techniques partition both pre-layout and post-layout circuits. If a post-layout circuit has different simulation results from a pre-layout circuit, the techniques determine where and how “cross-talk” of the RC networks due to RC extraction is changing the circuit physics behavior from the original design of the circuit. A flow of the local circuit simulation of the pre-layout netlist and the post-layout netlist of the same design is presented. A flow of reference or relative or differential circuit simulation of a known design and a new design of the same kind is described. This Abstract is not intended to limit the scope of the claims.

Abstract: A method for processing a source code file comprises scanning the source code file to identify text lines, and analyzing, via one or more processors, the text lines with a classifier to identify one or more of the text lines that correspond to code construct type information. The code construct type information includes license information. The classifier is trained with sample source code files. The method further comprises generating a subset of the text lines that excludes the one or more of the text lines identified as corresponding to the code construct type information. Further, the method comprises determining first text lines within the subset that correspond to open source code by comparing the subset to a database. The database includes a plurality of text lines associated with open source code.

Abstract: In one aspect, a method includes invoking a signoff tool via a first command from an implementation tool running on a register transfer level (RTL) design, and executing a native command of the signoff tool from within the implementation tool. The native command generates a notification. The method also includes determining whether the RTL design passes a low-power signoff check based on the notification and sending the design for final signoff verification based on the determination that the RTL design passes the low-power signoff checks.

Abstract: A method and system for performing duty-cycle correction (DCC) on a clock signal is provided. The method provides a two-step duty cycle correction. The method can include performing a main DCC of a single-ended clock signal, to generate a duty cycle adjusted single-ended clock signal, wherein a duty cycle of the single-ended clock signal is corrected according to a received duty-cycle continuous control signal and converting the duty cycle adjusted single-ended clock signal to differential clock signals. The method can further include performing a trim DCC by correcting a duty cycle of the differential clock signals according to a duty-cycle trim control signal received and generated in dependence upon duty cycles detected from differential output clock signals to provide error-corrected differential clock signals.

Abstract: A communication device includes controller circuitry and transmitter circuitry. The controller circuitry determines a number of strings of consecutive ones in a data packet, and determines a number of stuffed bytes based on the number of strings of consecutive ones. Further, the controller circuitry schedules a transaction packet to be transmitted within a bus interval based on a determination that a total number of bytes of the transaction packet is less than a number of available bytes in the bus interval. The total number of bytes of the transaction packet is based on a number of payload bytes of the data packet and the number of stuffed bytes. The transmitter circuitry transmits the transaction packet during the bus interval based on the controller circuitry scheduling the transaction packet for transmission.

Abstract: Disclosed herein are system, computer-implemented method, and computer program product (computer-readable storage medium) embodiments for implementing an intelligent DevSecOps workflow. An embodiment includes receiving, by at least one processor, a risk profile associated with a software deployment, and an update related to the software deployment; and evaluating, by the at least one processor, at least one parameter associated with the update, to produce an evaluation result. Additionally, the at least one processor may determine a set of actions in response to the update, based at least in part on the evaluation result, an application dataset corresponding to the software deployment, and a group of specified criteria on which the risk profile is based; or perform at least one action of the set of actions in response to the update, according to some example use cases.

Abstract: A system and method for performing a store to load process includes receiving a first store instruction. The first store instruction includes a first target address, a first mask, and a first data structure. Further, the first target address, the first mask, and the first data structure are stored within a first store buffer location of a store buffer. A first entry identification associated with the first store buffer location is stored within an age buffer. The first data structure is output based on an order of entry identifications within the age buffer.

Abstract: Described is technology for automatically generating a routing for an integrated circuit (IC) design. Information describing pin-pairs of an integrated circuit (IC) design is received. An initial routing of the IC design is determined by (i) defining connected wires between each pin-pair in the set of pin-pairs, and (ii) evaluating a target resistance for the pin-pair over the connected wires, wherein each connected wire is routed with other connected wires. A resistance adjustment is applied to adjust wire resistance of the connected wires of the initial routing. The resistance adjustment can be based on a square routing in response to a wire resistance being below the target resistance; or the resistance adjustment can be based on a multi-layer stacking in response to the wire resistance being above the target resistance. The routing is provided in patterns as generated by the initial routing and the resistance adjustment.

Abstract: A system performs static program analysis with artifact reuse. The system identifies artifacts associated with the software program being analyzed. The system processes the identified artifacts for performing static program analysis and transmits either the artifacts or identifiers for the artifacts to a second processing device for performing program analysis. The second processing device receives the artifacts and uses the received identifiers to retrieve the artifacts from a networked storage system. The second device also retrieves stored summaries of previous program analysis from the networked storage system. The program analysis uses the retrieved artifacts to generate work units for static program analysis. The analysis is performed only for those work units that are determined to remain unchanged from previous static program analysis cycles.