Abstract: A system and method for performing circuit design analysis obtains a circuit design comprising cells. The cells are associated with cell types. Aging parameters of a core analytical model are determined for each of the cell types in the circuit design to generate a calibrated analytical model. Aging effects for the cells are determined based on the calibrated analytical model and target stress conditions. An aged timing model is determined for the cell types based on the aging effects, an unaged timing model, and the target stress conditions.

Abstract: An initial polarity associated with an element of an integrated circuit design is determined. Responsive to a determination that an optimization process associated with the integrated circuit design is completed, a current polarity associated with the element is determined. A determination is made that a signal is to be applied at the element based on activity data associated with the integrated circuit design. The signal is associated with a first activity. Responsive to a determination that the current polarity associated with the element does not correspond to the initial polarity associated with the element, the single applied to the element is inverted. The inverted signal is associated with a second activity that is inverted from the first activity.

Abstract: A memory cell with dynamic disturb reduction includes first and second inverters in a cross-coupled arrangement, a write circuit to write to the memory cell, a read circuit to read the memory cell, and an interrupt circuit to disable at least a portion of the first inverter when the read circuit reads the memory cell.

Abstract: The present disclosure describes systems and methods for assigning nodes in a circuit design to layers. The method includes identifying a plurality of structures in a circuit design. Each of the plurality of structures includes four nodes of the circuit design and each of the four nodes are connected to every other node in the respective structure. The method also includes removing, from the plurality of structures, an even number of pairs of connected nodes of the circuit design to form a reduced node structure and assigning circuit layers for the nodes in the reduced node structure. The method further includes assigning, by a processing device, circuit layers for the pairs of connected nodes removed from the plurality of structures based on the assigned circuit layers for the nodes in the reduced node structure.

Abstract: A method of verifying connectivity in a circuit design, includes, in part, receiving a netlist of the circuit design; designating a plurality of destination nodes associated with the netlist; for each of the plurality of destination nodes, identifying one or more source nodes that are traversed from the destination node; for each source node identified as traversed from the destination node: transforming the netlist by including a first multiplexer having a first input terminal receiving a first variable logic value and an output terminal coupled to the source node; and enabling the first multiplexer to pass the first variable value to the destination node from the source node in order to check for connectivity between the source node and the destination node.

Abstract: The present disclosure describes systems and methods for generating a superconducting electronic circuit design. The system includes a memory and a processor. The processor simulates a superconducting electronic circuit design using a first process variation to produce a first score and simulates the superconducting electronic circuit design using a second process variation to produce a second score. The processor, in response to determining that the first score is lower than the second score, simulates the superconducting electronic circuit design using the first process variation and a first design variation to produce a third score and simulates the superconducting electronic circuit design using the first process variation and a second design variation to produce a fourth score. The processor updates the superconducting electronic circuit design using the first process variation and the first design variation in response to determining that the third score is higher than the fourth score.

Abstract: A system receives assertions representing properties of a circuit design. The system determines a representation of an alternating Büchi automaton based on the assertions. The system transforms the representation of the alternating Büchi automaton to generate a representation of a simplified alternating Büchi automaton. The simplified alternating Büchi automaton has fewer states than the alternating Büchi automaton. One or more states of the simplified alternating Büchi automaton are obtained by merging states of the alternating Büchi automaton representing the assertions of the circuit. The system performs formal verification of the circuit design using the simplified alternating Büchi automaton.

Abstract: Feature images representing a layout geometry of a lithographic mask are received. Mask function (MF) contributions from individual feature images are calculated by convolving the feature image with a corresponding three-dimensional mask (M3D) filter. The M3D filters represent an electromagnetic scattering effect of that feature image. At least one M3D filter also accounts for effects arising from a fabrication process for the lithographic mask.

Abstract: A circuit including: a memory cell connected to a first power supply configured to supply a first power supply voltage; a first bleeder transistor coupled between a first node of the memory cell and ground; and a second circuit coupled to a gate electrode of the first bleeder transistor and configured to supply a bleeder signal to control the first bleeder transistor in response to a drop in the first power supply voltage, wherein the first bleeder transistor is configured to discharge the memory cell in response to receiving the bleeder signal.

Abstract: An example non-transitory computer readable medium includes stored instructions which, when executed by a processor, cause the processor to convert an input clockwide pulse received from an upstream circuit running in a first clock domain into an output clockwide pulse that is synchronized to a second clock domain. The instructions further cause the processor to advance a count in response to the output clockwide pulse that is synchronized to the second clock domain.

Abstract: Design metrics from the physical design of an integrated circuit are made available to the front end designer. Physical design metrics are computed for sub-circuits from the physical design of an integrated circuit. Examples of physical design metrics include metrics for timing, congestion, power consumption and other metrics that depend on physical aspects of the circuit. Correspondence between the sub-circuits and register transfer level (RTL) source elements from RTL source code for the integrated circuit are determined. Examples of RTL source elements include individual lines of RTL source code, modules in the RTL source code, and user-defined constructs in the RTL source code. For different RTL source elements, the physical design metrics for the corresponding sub-circuits are aggregated. These aggregated physical design metrics, including the associations to the corresponding RTL source elements, are made available to users, for example front end designers.

Abstract: Test patterns are generated to test for a specified defect in an analog circuit by applying a succession of different strategies. Each strategy efficiently determines nominal responses and defect responses of the analog circuit to trial test patterns. The nominal response is a response of the analog circuit without the specified defect, and the defect response is a response of the analog circuit with the specified defect. Test patterns are selected based on differences between the nominal and defect responses.

Abstract: Disclosed herein are apparatus, method, and computer-readable storage device embodiments for implementing deconvolution via a set of convolutions. For example, an apparatus includes a memory and at least one processor, communicatively coupled with the memory, to perform operations including obtaining a tensor representing image data, generating a deconvolution segment of a plurality of deconvolution segments by performing a convolution to transform the tensor based at least in part on a convolution filter and a stride value, and generating a complete deconvolution for image processing by assembling each deconvolution segment of the plurality of deconvolution segments.

Abstract: An inductor structure includes a first inductor and a second inductor. A first portion of the first inductor is disposed on a first layer and a second portion of the first inductor is disposed on a second layer. A first portion of the second inductor is disposed on the first layer and a second portion of the second inductor is disposed on the second layer. The first portion of the first inductor and the second portion of the second inductor at least partially overlap. The second portion of the first inductor and the first portion of the second inductor at least partially overlap.

Abstract: A method for approximating an activation function, the method including: receiving an input value of the activation function; determining that the input value is within a range, the range includes a set of non-uniform intervals; determining a selected interval from among the set of non-uniform intervals including the input value; retrieving, by a hardware accelerator, from a look-up table (LUT) associated with a type of the activation function, values of one or more quadratic interpolation parameters associated with the selected interval; performing a quadratic interpolation on the input value to approximate the input value using the values of the one or more quadratic interpolation parameters; and determining a first approximated output of the activation function based on a result of the quadratic interpolation performed on the input value.

Abstract: At least one processor may obtain a plurality of test pattern data sets for a plurality of cores of an integrated circuit to be applied via a shared testing input bus. The at least one processor may next generate a test data sequence including an interleaving of respective task procedures of the plurality of test pattern data sets, where the generating of the test data sequence includes generating sleep instructions for respective cores of the plurality of cores in accordance with the interleaving. The at least one processor may then apply the test data sequence via the shared testing input bus.

Abstract: Built-in self-test (BIST) may be run on a set of circuits in proximity to a circuit under test (CUT) in an integrated circuit (IC) chip to generate noise and voltage drop conditions in the CUT. BIST may be run on the CUT while BIST is running on the set of circuits. A result of running the BIST on the CUT may be determined. The result may be associated with the noise and voltage drop conditions.

Abstract: An example is a method. A first logical value is written to a latch node of a latch circuit of a half static random access memory (SRAM) cell. A second logical value is read from the latch node. The latch circuit is non-inverter-based. The latch circuit includes a p-type transistor and an n-type transistor. A drain node of the p-type transistor is electrically connected to a gate node of the n-type transistor, and a drain node of the n-type transistor is electrically connected to a gate node of the p-type transistor. According to some examples, the half SRAM cell may be implemented as a storage node, for a physical unclonable function (PUF), and/or for data padding.

Abstract: A system and method for performing digital calibration of non-linearity in a circuit is presented. The circuit includes a phase detector, a statistics gathering device, and a feedback device. The phase detector provides information regarding a relationship between a clock from the programmable clock phase circuit and a reference signal. The statistics gathering device is coupled to the phase detector. The statistics gathering device receives an output of the phase detector to measure linearity of the programmable clock phase circuit. The feedback device is coupled to the statistics gathering device. The feedback device controls a delay and adjusts a phase of the clock based on measured values received from the statistics gathering device.

Abstract: Disclosed are techniques for simulation of a circuit design using a set of primary signals captured by a hardware emulation system. In preparation for simulation, the circuit design is divided into partitions that are substantially uniform in size. Sequential dependencies are then identified based on signals that cross partitions. The set of primary signals includes signals that, when provided as input to the simulation, break the sequential dependencies such that each partition can be simulated independently. Techniques for determining which signals to include in the set of primary signals are also disclosed. The hardware emulation system is configured to capture values of the primary signals as part of emulating the circuit design. Afterwards, the simulation is performed using the captured values. During the simulation, non-primary signals are reconstructed using values obtained from simulating each partition independently.