Abstract: A level shifter implemented with contention mitigation is disclosed. The level shifter generally includes: an input transistor pair; a first cascode transistor pair coupled in cascode with the input transistor pair, respectively; first cross-coupled transistors; a second cascode transistor pair coupled in cascode with the first cross-coupled transistors, respectively; a first level shifter transistor pair having gates coupled to drains of the second cascode transistors pair, respectively; and a first contention mitigation transistor pair coupled between a first reference voltage node and the first level shifter transistor pair, respectively.

Abstract: A plurality of design iterations are executed for a flow to design a circuit. The design flow includes a sequence of at least two stages. Each stage produces an output design of the circuit from an input design of the circuit, in accordance with parameters for that stage. The design iterations select parameter values for slices of one or more stages of the design flow. In the design iterations for at least one of the slices, parameter values for a non-final stage of the design flow are selected based on a final quality of result (QoR) of the design flow. The design iterations for this slice are adapted based on final QoRs produced by the design iterations.

Abstract: Failsafe IO circuitry is provided that can operate in a failsafe mode and a normal mode. The failsafe IO circuitry can include input circuitry that (i) receives a pad signal (PAD) from driver circuitry, (ii) receives control signals (VDDIO, VREFN) and (iii) provides an output signal (PADBY2) generated based on the received control signals (VDDIO, VREFN), wherein, when operating in a normal mode, the pad signal (PAD) is a floating signal and the output signal (PADBY2) is 0 volts (0V), and power gated logic circuitry that (i) receives the output signal (PADBY2) from the input circuitry, (ii) receives the control signals (VDDIO, VREFN) and (iii) outputs a reference pad failsafe signal (PAD_FS), wherein, when operating in the normal mode, the reference pad failsafe signal (PAD_FS) is 0V.

Abstract: The present disclosure describes systems and methods for generating timing libraries. The apparatus includes a memory and a processor. The processor determines a condition that indicates whether a superconducting electronic circuit design passes or fails logic verification and determines an edge-of-failure value for a timing parameter for the superconducting electronic circuit design. The processor simulates the superconducting electronic circuit design using the edge-of-failure value for the timing parameter and a first process variation to produce a first timing value for the superconducting electronic circuit design and simulates the superconducting electronic circuit design using the edge-of-failure value for the timing parameter and a second process variation to produce a second timing value for the superconducting electronic circuit design.

Abstract: An N-bit successive SAR includes, in part, a differential comparator receiving a pair of differential input signals and generating a pair of differential comparator output signals; an N-bit register storing the comparator output signals; a capacitive DAC supplying differential feedback signals to the differential comparator in response to the register; and M detection circuits each associated with one of M most significant bits of the N-bit register. Each detection circuit includes: a PMOS transistor precharging a first node to a supply voltage; a first NMOS transistor having a drain coupled to the first node, and a gate receiving a first voltage representative of one of the differential feedback signals; a second NMOS transistor having a drain coupled to a source of the first NMOS transistor, a gate receiving a second voltage representative of the other one of the differential feedback signals, and a source coupled to a ground terminal.

Abstract: A method of performing elliptic curve cryptography includes, in part, receiving a scalar k representative of a secret key; and splitting, by a processing device, a multiplication of k by a generator point P on the elliptic curve ([k]P) into a sum of a first multiplication defined by [k?r]P, and a second multiplication defined by [r/n](nP), where n is a power of 2 of an integer number, and r is an integer smaller than k/(2*n); i.e., r<k(/2*n).

Abstract: A circuit includes, in part, a transconductance amplifier, a common source amplifier, a resistor, and NMOS transistor. The common source amplifier is coupled to an output of the transconductance amplifier and generates a signal coupled to an output terminal of a crystal oscillator circuit. The resistor is coupled between the transconductance amplifier and the ground terminal. The NMOS transistor has a drain terminal coupled to a first terminal of the first resistor, a source terminal coupled to a second terminal of the first resistor, and a gate terminal coupled to an input terminal of the common source amplifier and to an input terminal of the crystal oscillator circuit.

Abstract: A method includes: receiving an input job associated with a license type; receiving a license server order including a plurality of license servers; reading license server information regarding the plurality of license servers from a license server information cache; updating, by a processing device, the license server order based on the license server information to compute an updated license server order; and accessing at least one of the plurality of license servers in the updated license server order to attempt license checkout of a license from one of the plurality of license servers, the license being appropriate for the license type of the input job.

Abstract: A method, a system, and a non-transitory computer readable medium for simulating a circuit are provided. The method includes generating a digital simulation file for the circuit that includes a block, generating a mixed simulation file for the circuit, generating a waveform file by executing the digital simulation file for a first time window of a simulation, determining a plurality of analog values for the block based on the waveform file, and executing, by a processor, the mixed simulation file for a second time window of the simulation with the plurality of analog values annotated to the block at a start of the second time window. The digital simulation file corresponds to the block in a digital view and the mixed simulation file corresponds to the block in an analog view.

Abstract: Josephson junction (JJ) structures are disclosed. In some embodiments, a JJ structure may include alternating planar superconducting structures and planar non-superconducting structures arranged along a direction away from a wafer surface.

Abstract: A first profile associated with a first circuit may be obtained by running a first test (which may be a shmoo test) on the first circuit. Running the first test on the first circuit may include: selecting an operating condition for testing the first circuit, where the operating condition includes noise and voltage drop conditions to be used during testing; selecting a set of circuits in proximity to the first circuit based on the noise and voltage drop conditions; running built-in self-test (BIST) on the set of circuits to generate the noise and voltage drop conditions in the first circuit; running BIST on the first circuit while BIST is running on the set of circuits; determining a first result of running the BIST on the first circuit; and associating the first result with the operating condition.

Abstract: A design database contains register transfer level (RTL) code for a design, and a violations database contains violations generated by a static analysis of the RTL code. The violations are tagged to code snippets of the RTL code. A machine learning model executes on a processing device. The machine learning model generates recommendations for waivers of the violations, based on the violations and the corresponding tagged code snippets in the databases.

Abstract: A method of performing static timing analysis for a circuit design includes, in part, identifying a multitude of logic blocks of the circuit design matching a design pattern; determining values of a multitude of electrical properties associated with a first logic block representative of each of the plurality of logic blocks; and determining, during the static timing analysis, a delay associated with each of the multitude of logic blocks using the values of the electrical properties.

Abstract: A directed acyclic graph (DAG) and an extended regular expression (ERE) may be received. A circuit design may be generated based on the DAG. A cover property may be generated based on the ERE. The circuit design may be simulated. A first result may be determined based on whether the cover property is satisfied during the simulating the circuit design. It may be determined whether the ERE matches a path in the DAG based on the first result.

Abstract: A method for performing a computation associated with a layout of a circuit design includes, in part: generating a graph having a multitude of nodes disposed across a multitude of layers associated with the layout, wherein each node corresponds to a polygon in the layout, wherein the multitude of nodes includes a source node and a sink node; traversing from the source node to the sink node via the nodes in accordance with a rule enabling traversal between one or more of (i) nodes disposed in the same layer, and (ii) from a first node disposed in one of the layers to a node disposed in another layer that is higher than the first layer; pruning nodes that are not visited during the traversal; and maintaining nodes that are not pruned for use in the computation.

Abstract: An example is a method. A pseudo array supply voltage (VDDAI) of a bitcell power tracking column for a memory array is determined by a write assist circuit coupled to the memory array. An actual VDDAI provided to a bitcell in the memory array during a write operation, based on the pseudo VDDAI of the bitcell power tracking column, is tracked by the write assist circuit. A collapse level of the actual VDDAI to the bitcell is controlled during the write operation, based on the tracking.

Abstract: An example is a method. A query challenging authenticity is received at an intellectual property (IP) block in an integrated circuit (IC) die. The query may be a query of a query-response pair. A response to the query is generated, at the IP block, using a logic built-in self-test (LBIST) circuit. The response is transmitted from the IP block. The response may be received and compared to an expected response of the query-response pair. Authenticity may be validated when the response matches the expected response.

Abstract: A method includes: receiving an integrated circuit design including a plurality of cells; performing a first plurality of design rule checks on a first portion of the plurality of cells of the integrated circuit design based on a sequence of design rule checkers arranged in a first order; collecting data on an execution of the design rule checkers on the first portion of the plurality of cells; updating, by a processing device, the sequence of design rule checkers, based on the data, to a second order of design rule checkers; and performing a second plurality of design rule checks on a second portion of the plurality of cells of the integrated circuit design based on the sequence of design rule checkers arranged in the second order.

Abstract: A photonic integrated circuit (PIC) may be simulated by executing multiple iterations. Each iteration estimates outputs of the components in the PIC from inputs to the components. At least one output is estimated by running a simulation of the component. For at least one component and one iteration, the input for the current iteration is compared against a cached input for the component. Based on the comparison, it is determined whether to retrieve a corresponding cached output for the component or to run the simulation of the component.

Abstract: An SRAM cell includes four PMOS and four NMOS transistors. The first PMOS and NMOS form a first inverter. The second PMOS and NMOS form a second inverter having an output coupled to an input (first node) of the first inverter, and an input coupled to an output (second node) of the first inverter. The third NMOS has its source coupled to the second node, drain coupled to a first bitline, and gate coupled to a third node. The fourth NMOS has its source coupled to the first node, drain coupled to a second bitline, and gate coupled to a fourth node. The third PMOS has its drain coupled to the first node, source coupled to the second bitline, and gate coupled to a fifth node. The fourth PMOS has its drain coupled to the second node, source coupled to the first bitline, and gate coupled to a sixth node.