Abstract: An SRAM cell includes four PMOS and four NMOS transistors. The first PMOS and NMOS form a first inverter. The second PMOS and NMOS form a second inverter having an output coupled to an input (first node) of the first inverter, and an input coupled to an output (second node) of the first inverter. The third NMOS has its source coupled to the second node, drain coupled to a first bitline, and gate coupled to a third node. The fourth NMOS has its source coupled to the first node, drain coupled to a second bitline, and gate coupled to a fourth node. The third PMOS has its drain coupled to the first node, source coupled to the second bitline, and gate coupled to a fifth node. The fourth PMOS has its drain coupled to the second node, source coupled to the first bitline, and gate coupled to a sixth node.

Abstract: A constant transconductance-resistance (gmR) tracking biasing circuit includes: a first p-type metal oxide semiconductor (pMOS) transistor and a second pMOS transistor connected to form a first current mirror; and a first n-type metal oxide semiconductor (nMOS) transistor and a second nMOS transistor connected to form a second current mirror, the constant gmR tracking biasing circuit being configured to generate a bias output signal in accordance with currents flowing through the first pMOS transistor, the second pMOS transistor, the first nMOS transistor, and the second nMOS transistor, and the bias output signal being configured to control a pMOS transconductance of an input pMOS transistor and an nMOS transconductance of an input nMOS transistor of an analog circuit.

Abstract: A method includes obtaining a target integrated circuit (IC) layout, accessing a repository, identifying a device within the target IC layout by matching an area of the target IC layout to a source pattern, and replacing at least a portion of the area of the target IC layout with a replacement pattern. The repository stores the source pattern for the device and the replacement pattern corresponding to the source pattern.

Abstract: A circuit includes a PMOS transistor having a source terminal coupled to a first node and a drain terminal coupled to a second node; a first programmable memristor having a first terminal coupled to the first node and a second terminal receiving a first voltage; and a first select transistor having a terminal coupled to the first node, a second terminal coupled to a third node adapted to receive a second voltage, and a gate terminal receiving a first select signal. The resistance of the first programmable memristor is responsive to a difference between the first and second voltages to change a pullup strength of the PMOS transistor. The circuit may further include a NMOS transistor; a second programmable memristor and a second select transistor. The resistance of the second programmable memristor may be changes using the second select transistor to change a pulldown strength of the NMOS transistor.

Abstract: A voltage driver for supplying a supply voltage includes multiple PMOS transistors, multiple NMOS transistors, a pad, impedance divider circuits, NMOS clampers, PMOS clampers, a gate protection circuit, and a bulk protection circuit. A maximum of the supply voltage is N times a maximum of the drain-source voltage of each transistor. The pad is configured to receive a voltage signal for dynamically controlling gates of a subset of the NMOS transistors and a subset of the PMOS transistors. The impedance divider circuits are configured to generate voltage signals. The NMOS clampers and PMOS clampers are configured to receive reference voltages and limited voltage signals to generate output. The gate protection circuit are between outputs of the clampers and gates of the transistors. The bulk protection circuit is between bodies of the transistors and the impedance divider circuit.

Abstract: A processing device determines cell boundary conditions for each of a plurality of boundaries of a cell in an integrated circuit layout and determines a layout dependent effect (LDE) impact for the cell based on the cell boundary conditions for each of the plurality of boundaries of the cell. The processing device further generates a prediction of an LDE impact on one or more contents of a library associated with the cell, and performs an LDE-aware timing analysis for the cell based on the prediction of the LDE impact on the one or more contents of the library.

Abstract: The present disclosure describes a system and method for determining a function for a quality of results (QoR) for a circuit design. The method includes receiving a circuit design that includes a first node, a second node, and a connection between the first node and the second node in a design space, placing an array of points within the design space, sampling first field values of the circuit design at each point of the array of points, and determining a first sampled function based on the first field values. The method includes moving the array of points within the design space, sampling second field values of the circuit design at each point of the array of points, determining a second sampled function based on the second field values, and determining a function based on the first and second sampled functions. The function produces a QoR for the circuit design.

Abstract: A method of simulating a mixed-signal circuit design, includes, dividing a first circuit disposed in a first level of hierarchy of the circuit design into a multitude of subcircuits. At least a first subcircuit processes an electrical signal, and at a least a second subcircuit processes an optical signal; adding one or more input/output terminals to the first subcircuit to transform the subcircuit into a first subblock; adding one or more input/output terminals to the second subcircuit to transform the second subcircuit into a second subblock; replacing an instance of the first circuit design in a second level of hierarchy of the mixed-signal design with the first and second subblocks; simulating the first subblock in each of the first and second levels of the hierarchy using an electrical circuit simulator; and simulating the second subblock in each of the first and second levels of the hierarchy using an optical simulator.

Abstract: A memory device may include first and second inverters cross-coupled in a feedback loop, a first access transistor for a first node of the feedback loop, a second access transistor for a second node of the feedback loop, where the first node and the second node are to store complementary binary data bit values, and a bidirectional threshold switching device in the feedback loop between an output of the second inverter and an input of the first inverter. An additional memory device may include first and second inverters cross-coupled in a feedback loop, a first access transistor for a first node of the feedback loop, a second access transistor for a second node of the feedback loop, where the first node and the second node are to store complementary binary data bit values, and a bidirectional threshold switching device between the first access transistor and the first node.

Abstract: A method includes determining a plurality of threshold margins corresponding to a plurality of functional paths in an electronic circuit. The method further includes storing the plurality of threshold margins corresponding to the plurality of functional paths in a memory. The method further includes receiving a first trigger from a processing device. The method further includes responsive to receiving the first trigger, monitoring at least one of the plurality of threshold margins corresponding to at least one of the plurality of functional paths in view of a previously determined threshold margin stored in the memory and corresponding to the at least one of the plurality functional paths.

Abstract: An integrated circuit (IC) design layout may be partitioned into a set of content areas. A content area in the set of content areas may be divided into a set of zones based on an image-based representation of the content area. A repetition unit may be identified in a zone in the set of zones, where the repetition unit is a portion of the zone, and where the zone includes multiple instances of the repetition unit. A skeleton layout may be generated corresponding to the IC design layout, where the skeleton layout specifies locations of the multiple instances of the repetition unit in the IC design layout.

Abstract: A testbench for a design under test (DUT) includes components used to verify functionality of the DUT through simulation of the DUT. The components are grouped into component groups, and the components within an individual component group are executed on a same thread of the simulation. The component groups are also executed on a single thread, which includes logging accesses to memory by different component groups. Based on the logged memory accesses, a processing device identifies whether any component groups create a thread data race. An action is taken in response to identifying thread data races.

Abstract: Aspects of the present disclosure relate to improving runtime performance of equivalence checkers by a shift left process that uses an RTL lint tool to identify RTL code that can be a source of verification complexity for the downstream equivalence checker. The RTL code is further compared to a corresponding circuit model to determine a potential gate-level location of the potentially problematic RTL code. A weight can be calculated to represent a level of verification complexity that may be generated by the particular portion of the RTL code. Further, one or more recommendations can be generated by the RTL lint tool to prevent some of the verification complexity for the downstream equivalence checker.

Abstract: Systems and methods for load compensation are presented to support a wide range of capacitive loads on a pad coupled to an I/O transmitter. The I/O transmitter includes I/O architecture coupled to a pad and a calibration circuit coupled to the I/O architecture. The calibration circuit includes sensing circuitry, pulse generation circuitry coupled to the sensing circuitry and control bit generation circuitry coupled to the pulse generation circuitry. The control bit generation circuitry generates control bits proportional to load variations detected at the pad and feeds the control bits to the I/O architecture to modulate rise and fall times of pulsed signals at the pad.

Abstract: A first set of ports and/or circuit elements in a circuit design may be received, where the first set of ports and/or circuit elements is expected to cause damage if the first set of ports and/or circuit elements is compromised. A second set of ports and/or circuit elements in the circuit design may be determined by performing forward path tracing from the first set of ports and/or circuit elements, backward path tracing from the first set of ports and/or circuit elements, or both forward and backward path tracing from the first set of ports and/or circuit elements. A report may be generated based on the second set of ports and/or circuit elements in the circuit design, where the report is used for performing threat analysis and risk assessment for the circuit design.

Abstract: A method and system are provided for placing cells in a circuit design layout. The method includes placing the cells at candidate locations in the circuit design layout in accordance with design rules, and determining, for each location, a probability of design rule success for the placement of each cell of the cells based on one or more of the available candidate locations.

Abstract: A first set of timing paths may be selected in an integrated circuit (IC) design. A first set of timing slack values may be calculated for the first set of timing paths across a first set of corners. A dominant corner may be selected in the first set of corners based on the first set of timing slack values. A second set of timing slack values for the dominant corner may be determined for a second set of timing paths in the IC design. A third set of timing slack values may be estimated for the second set of timing paths for non-dominant corners. The third set of timing slack values may be used to select a second set of corners for a timing path in the second set of timing paths, and circuit objects in the timing path may be marked with the second set of corners.

Abstract: A time division multiplexing (TDM) device includes a first first-in-first-out (FIFO) circuit configured to receive a user clock signal and a user data signal from a plurality of inputs, a transmitter circuit operatively coupled to the first FIFO circuit in a fast clock domain, the transmitter circuit including one or more multiplexing state machines, the one or more multiplexing state machines configured to receive a plurality of input signals from the plurality of inputs, multiplexing the input signals to form a multiplexed signal, and transmitting the multiplexed signal using a fast clock, a receiver circuit including one or more demultiplexing state machines, the one or more demultiplexing state machines configured to receive the multiplexed signal, and a second FIFO circuit configured to output the user data signal to the plurality of outputs.

Abstract: Generating an integrated circuit (IC) includes receiving Design For Testability (DFT) Compressor Decompressor (CODEC) circuitry of an integrated circuit (IC) design, and partitioning the DFT CODEC circuitry into two or more sub-blocks based on a number of scan chains within the IC design. Further, scan chains are assigned to each of the two or more sub-blocks based on locations of end points within the scan chains. A layout of the IC design is generated by placing the DFT CODEC circuitry within the IC design based the locations of end points within the scan chains and the assigned scan chains to each of the two or more sub-blocks.

Abstract: A method of verifying a logic circuit design by a hardware emulation system, includes, in part, receiving a netlist of the logic circuit design configured to operate in response to positive edges of a first clock signal, and transforming each of a first multitude of flip-flops disposed in the logic circuit design to a dual-enable flip-flop configured to operate in response to positive edges of a second clock signal thereby to generate a transformed logic circuit design. The state of the logic circuit design after 2k cycles of the first clock is the same as a state of the transformed logic circuit design after k cycles of the second clock.