Abstract: An apparatus for processing an input signal from a memory includes an attenuator circuit and an analog front end (AFE) circuit. The attenuator circuit attenuates the input signal from the memory to produce an attenuated signal. The AFE circuit includes a first amplification stage and a second amplification stage. The first amplification stage has an n-type metal-oxide semiconductor (NMOS) transistor. The NMOS transistor has a gate that receives the attenuated signal from the attenuator circuit. The second amplification stage has a p-type metal-oxide semiconductor (PMOS) transistor. The PMOS transistor has a gate that receives the attenuated signal from the attenuator circuit. Outputs of the first amplification stage and the second amplification stage are electrically coupled to a common output of the AFE circuit.

Abstract: A computational lithography process uses machine learning models. An aerial image produced by a lithographic mask is first calculated using a two-dimensional model of the lithographic mask. This first aerial image is applied to a first machine learning model, which infers a second aerial image. The first machine learning model was trained using a training set that includes aerial images calculated using a more accurate three-dimensional model of lithographic masks. The two-dimensional model is faster to compute than the three-dimensional model but it is less accurate. The first machine learning model mitigates this inaccuracy.

Abstract: Poly-bit cells and methods for forming the same are provided. In one example, a method for forming a poly-bit cell includes identifying layouts in a library of single-bit cells having one or more of a different functionality and a different drive that are combinable; storing, in memory, layouts that are combinable; and creating layouts of poly-bit cells from the stored combinable single-bit cells. Each poly-bit cell combined from layouts of at least two single-bit cells has one or more of a different functionality and a different drive.

Abstract: Phase detector circuitry includes first mixer circuitry configured to receive a first clock signal and a second clock signal. The first mixer circuitry includes a first plurality of transistors. The first plurality of transistors includes first transistors, second transistors, and an output transistor. The first transistors receive the first clock signal, and the second transistors receive the second clock signal. The first output transistor outputs a first output signal. The first output signal corresponds to a first phase difference between the first clock signal and the second clock signal.

Abstract: Operations to recognize clock ports within a simulation circuit component and/or recognize a clock signal within simulation waveforms are described. One or more of the operations include generating a plurality of output values at an output port of a circuit simulation component by applying, during a simulation, a plurality of input values to a first input port of the circuit simulation component. The operations also include calculating a correlation vector based on bit sequences in the input values and bit sequences in the output values. The first input port is determined to be a clock port by applying a machine learning model to the correlation vector.

Abstract: A system generates a mask for a circuit design while enforcing symmetry and consistency across random areas of the mask. The system builds a mask solutions database mapping circuit patterns to mask patterns. The system uses the mask solutions database to replace circuit patterns of the circuit design with mask patterns. The system identifies properties in circuit patterns of the circuit design and enforces the same property in the corresponding mask patterns. Examples of properties enforced include symmetry within circuit patterns and similarity across circuit patterns. The system combines mask patterns in different regions of the circuit and resolves conflicts that occur when there are multiple masks within a region.

Abstract: A system and method are provided for driving a dual-rail memory circuit that operates with sensing of a memory bit cell, inversion of the sense signal and level shifting in four stage delays. The system includes inversion circuitry configured to (i) receive power from a first power rail (VDDA) of the dual-rail memory, (ii) receive an output of a sense amplifier that senses a state of a bit cell of the dual-rail memory, and (iii) provide two outputs (QB, QT) limited to the first power rail VDDA. The system further includes level-shifting circuitry configured to (i) receive the two outputs of the inversion circuitry (QB, QT). (ii) receive power from a second power rail of the dual-rail memory (VDDP) and (iii) drive an output (Q) in dependence on the two outputs of the inversion circuitry (QB, QT) and limited to the second power rail VDDP which is less than the first power rail VDDA.

Abstract: An example described herein is a circuit including a dynamic complementary metal-oxide-semiconductor (CMOS) inverter level translator circuit and a capacitor. The dynamic CMOS inverter level translator circuit is electrically connected to a first power domain and has a first input node configured to receive a first trigger signal generated in the first power domain. The dynamic CMOS inverter level translator circuit has a second input node configured to receive a second trigger signal generated in a second power domain different from the first power domain. The capacitor is electrically coupled to an output node of the dynamic CMOS inverter level translator circuit. The capacitor selectively charges to the first power domain through the dynamic CMOS inverter level translator circuit based on the first trigger signal. The capacitor selectively discharges to provide a negative coupling voltage to a write assist supply node.

Abstract: A method for dynamically adjusting transmit power of a first device that is in communication with a second device using a wireless communications protocol includes, in part, determining, by the second device, a received signal strength indication (RSSI) associated with a signal received from the first device; determining, by the second device, a first amount of power adjustment for the first device in accordance with the determined RSSI; transmitting the first amount of power adjustment from the second device to the first device; determining, by the first device, a second amount of power adjustment for the first device in accordance with the RSSI and the first amount of power adjustment; and changing a transmit power of the first device in accordance with the second amount of power adjustment.

Abstract: An output driver includes a pullup driver, a pulldown driver and a resistive element. The pullup driver includes a first PMOS transistor having a source coupled to a first supply voltage and a gate receiving a first data representative of a transmitted data, and a second PMOS transistor having a source coupled to a drain of the first PMOS transistor and a gate receiving a first analog signal. The pulldown driver includes a first NMOS transistor having a source coupled to a second supply voltage and a gate receiving a second data representative of the transmitted data, and a second NMOS transistor having a source coupled to a drain of the first NMOS transistor, a drain coupled to a drain of the second PMOS transistor, and a gate receiving a second analog signal. The resistive element is coupled between the drain terminal of the second NMOS transistor and a pad.

Abstract: A circuit includes: a first latch; a second latch coupled to the first latch; and a third latch coupled to the second latch at an input terminal of the second latch, wherein the third latch includes: a first inverter and a second inverter, the first inverter being coupled between the input terminal of the second latch and an input terminal of the second inverter and the second inverter being coupled between an output terminal of the first inverter and an input terminal of the first inverter; a first switch connecting the first inverter to a first voltage source; a second switch connecting the first inverter to ground voltage; a third switch connecting the second inverter to the first voltage source; a fourth switch connecting the second inverter to the ground voltage; and a fifth switch connecting the second latch and the first inverter.

Abstract: A method for timing path analysis using flow graphs. The method includes receiving timing data associated with an integrated circuit (IC) design. The timing data includes a plurality of timing paths. The method also includes generating a graphical representation of the plurality of timing paths. A timing path is represented as a flow ribbon across one or more components of the IC design. A display attribute of the flow ribbon is indicative of a metric of the timing path. The graphical representation is provided in a graphical user interface (GUI) to a user.

Abstract: A freeform optical surface includes, in part, an off-axis optical surface and a departure optical module. The off-axis optical surface may be an off-axis conic optical surface. The departure optical module may be substantially perpendicular to the off-axis conic optical surface.

Abstract: A bitcell of a one-time programmable memory includes: a write-once programmable circuit element and a node connected in series between a word line and a power rail; a select read device connected between the node and a bitline, the select read device having a gate electrode connected to a first signal line extending parallel to the word line; and a select write device connected between the word line and the power rail and in series with the write-once programmable circuit element and the node, the select write device having a gate electrode connected to a second signal line extending parallel to the bitline.

Abstract: A line driver circuit include a multitude of PMOS and NMOS transistors. A first PMOS transistor receives an output voltage of a first level converter. A second PMOS transistor receives a first reference voltage. A third and fourth PMOS transistors receive an output voltage of a second voltage level converter. The source terminal of the first PMOS transistor receives the supply voltage. The drain terminal of the fourth PMOS transistor is coupled to an output terminal of the line driver circuit. A first NMOS transistor receives an input signal. A second NMOS transistor receives a second reference voltage. A third and fourth NMOS transistors receive an output voltage of a third level converter. The first NMOS transistor receives a ground potential. The drain terminal of the fourth NMOS transistor is coupled to the output terminal of the line driver. The first, second and third voltage converters receive the input signal.

Abstract: An oscillator comprising a first oscillator circuit having a first inductive portion, a plurality of shared switches for selectively connecting a shared oscillator tuning circuit and a second oscillator circuit having a second inductive portion, the plurality of shared switches and the shared oscillator tuning circuit. In some embodiments, when the first oscillator circuit is active, the second oscillator circuit is inactive to allow the sharing of the shared oscillator tuning circuit.

Abstract: A system for executing tensor operations including: a programmable tensor processor; and a memory coupled to the programmable tensor processor, wherein the programmable tensor processor includes: one or more load AGU circuits to generate a first sequence of addresses and read input tensor operands from the memory based on the first sequence of addresses; a datapath circuit to perform the tensor operations on the input tensor operands based on receiving one or more instructions to determine output tensor operands, the one or more instructions being based on a loop iteration count and loop body micro-code instructions defining a loop body of a tensor program stored in the memory, the loop body micro-code instructions being executed in the programmable tensor processor; and a store AGU circuit configured to generate a second sequence of addresses and write the output tensor operands to the memory based on the second sequence of addresses.

Abstract: A method of detecting an error includes, in part, defining a bit pattern using a first multitude of bits, a second multitude of bits, the bits of an error correction code (ECC), and at least one user selected bit. The method further includes, in part, receiving a first value represented by the first multitude of bits and the at least one user selected bit; receiving a second value represented by the second multitude of bits; receiving a third value represented by the ECC bits. The method further includes, in part, generating a syndrome value from the first, second and third values; and using a subset of the syndrome value bits to detect the error in the first, second or third values. The third value is determined in accordance with the first and second values.

Abstract: A method includes: receiving an integrated circuit design including a plurality of sub-circuits and one or more clocks to be distributed to the sub-circuits; setting one or more constraints on generating a clock network for a selected clock of the one or more clocks of the integrated circuit design; building, by a processor, a clock tree graph for the clock network for the selected clock based on a cached initial clock tree graph stored in a memory connected to the processor, the clock tree graph comprising nodes corresponding to the sub-circuits; generating a pin topology for the clock network based on the clock tree graph and the integrated circuit design; and placing, based on the pin topology, one or more pins for the clock network at one or more sides of the sub-circuits within the integrated circuit design to generate a pin placement for the clock network.

Abstract: A method of testing a connectivity controller includes, in part, setting a configuration register disposed in the connectivity controller to a first value; causing a first data stored in a first section of a memory associated with the connectivity controller to be forwarded and pass through at least a first component of the connectivity controller and a second component of the connectivity controller, in sequence, in response to the first value; returning data received by the second component, via the first component, for storage in a second section of the memory; comparing, by a processor, the first data to the data returned and stored in the second section of the memory; and verifying the test if the first data matches the returned data.