Abstract: A Reed-Solomon decoder circuit includes: a syndrome calculator circuit to compute syndrome values for a first codeword and a second codeword sequentially supplied to the syndrome calculator circuit, where last symbols of the first codeword overlap with first symbols of the second codeword during an overlap clock cycle between: a first plurality of non-overlap clock cycles during which the first codeword is supplied to the syndrome calculator circuit; and a second plurality of non-overlap clock cycles during which the second codeword is supplied to the syndrome calculator circuit; an error locator and error evaluator polynomial calculator circuit; an error location and error value calculator circuit; an error counter; and an error corrector circuit to correct the errors in the first codeword and the second codeword based on error counts and the error magnitudes computed by an error evaluator circuit.

Abstract: A configuration to address a bus stall during data packet transmission also allows for bus recover due to data packet transmission errors. If a downstream node is not ready to receive data from a buffer of an upstream node, a timer counts a timeout value. The time count increments on each clock cycle in which the downstream node is not ready to receive data. The buffer is cleared at the upstream node when the count reaches a predetermined threshold value. Alternately, the configuration also operates to receive a packet header from an upstream node, the packet header identifying a number of data in a packet. If no data downstream is received on a clock cycle, a counter triggers and is incremented for each cycle in which no date is received. When a threshold is reached dummy data fills a data packet to then transmit the data.

Abstract: In some aspects, a graph is used to assist users in cause analysis of faults. The graph represents signal flow through a design of an integrated circuit The graph includes graph elements, such as nodes and edges. The nodes may represent cells and nets in the circuit design, and the edges may represent signal flow between the cells and nets. A propagation model for the propagation of faults through the graph is constructed. The propagation model includes local propagation models for the propagation of faults through the graph elements. Propagation of a known fault backward through the graph is modeled using the propagation model. This results in a causality ranking of the graph elements as possible causes of the known fault. Information indicative of the causality ranking is displayed in a user interface that shows the design of the integrated circuit.

Abstract: A method and apparatus for identifying net text in a net list at each hierarchical level of the net list is disclosed. The identified net text is then associated with the hierarchical level in which the net text was found. Each cell in the net list can then be optimized by exploding the net list of at least one cell. Once exploded, the identified net text together with the associated hierarchical level of each progeny cell of each exploded cell is associated with the net list of the exploded cell.

Abstract: Sets of objects may be received which are desired to be stored using a nested hash map, where the nested hash map may include multiple levels, and where each set of objects in the sets of objects may correspond to a level in the nested hash map. The nested hash map may be created from a bottom level of the nested hash map to a top level of the nested hash map, which may include: creating a first hash map at a first level of the nested hash map, creating a first shared pointer which points to the first hash map, and creating a second hash map at a second level which is immediately above the first level, where the second hash map maps at least one object to the first shared pointer.

Abstract: A first and second input tone are applied to a continuous-time complex filter within an integrated circuit. The magnitude of the output of the filter at the frequency of each of the first and second input tones are measured and compared to determine the value of a filter tuning control signal. A tuning control signal is applied to the filter with the determined value to tune the filter.

Abstract: A system and method access memory blocks in a memory by receiving a memory transaction request from a processing device. First hash bits of the memory transaction request are compared with second hash bits of a first memory block of a memory. Data associated with the first memory block is output to the processing device based on the comparison of the first hash bits with the second hash bits.

Abstract: A method includes identifying isolated shapes within a semiconductor design. The isolated shapes correspond to patterns of layers of components of the semiconductor design. The method also includes identifying one or more unique patterns among the isolated shapes, generating a virtual isolated pattern layer including data associated with the isolated shapes and the one or more unique patterns, determining whether a unique pattern of the one or more unique patterns satisfies a design rule based on the data of the virtual isolated pattern layer and producing an updated semiconductor design based on the determination that the unique pattern satisfies the design rule.

Abstract: A system and method for generating a netlist of a memory device includes receiving a logical netlist file including memory instances and placement information for the memory device. Each memory instance includes leaf cells. Further, a location of a first leaf cell and a location of a second leaf cell of the leaf cells of a first memory instance is determined based on the placement information. A first net segment between the first leaf cell and the second leaf cell is generated based on the location and parasitic elements of the first leaf cell and the location and parasitic elements of the second leaf cell. A parasitic netlist is generated based on the first net segment and the parasitic elements of the first leaf cell and parasitic elements of the second leaf cell.

Abstract: Disclosed herein are apparatus, method, and computer-readable storage device embodiments for implementing deconvolution via a set of convolutions. An embodiment includes a convolution processor that includes hardware implementing logic to perform at least one algorithm comprising a convolution algorithm. The at least one convolution processor may be further configured to perform operations including performing a first convolution and outputting a first deconvolution segment as a result of the performing the first convolution. The at least one convolution processor may be further configured to perform a second convolution and output a second deconvolution segment as a result of the performing the second convolution.

Abstract: A delay selector includes a first multiplexer, a first inverter, a second multiplexer, and a second inverter. The first multiplexer has a first input coupled to an input of the delay selector. The first inverter is coupled between the input of the delay selector and a second input of the first multiplexer. The second multiplexer has a first input coupled to an output of the first multiplexer. The second inverter is coupled between the output of the first multiplexer and a second input of the second multiplexer.

Abstract: Techniques for mixed precision quantization of a machine learning (ML) model. A target bandwidth increase is received (302), for the ML model (114) including objects of a first data type represented by a first number of bits. The target bandwidth increase relates to changing a first portion of the objects to a second data type represented by a second number of bits different from the first number of bits (310). The method further includes sorting the objects in the ML model based on bandwidth (304). The method further includes identifying the first portion of the objects to change from the first data type to the second data type, based on the target bandwidth increase and the sorting of the plurality of objects (508). The method further includes changing the first portion of the objects from the first data type to the second data type (508).

Abstract: Disclosed herein are computer-implemented method, system, and computer-program product (non-transitory computer-readable storage medium) embodiments for advanced register merging. A first register-merging operation may be configured to merge, into a first survivor register, a first plurality of registers of the RTL description. A second register-merging operation configured to merge, into a first equivalence class, a second plurality of registers that share a first functional equivalency based on output of the first register-merging operation. Any register in the first equivalence class as noted here may in turn be non-equivalent to any register in the second equivalence class. Equivalence of registers in a given class may be verified using simulations or satisfiability checks.

Abstract: Instance instrumentation is provided for different data sources by identifying an instance of a function in a program that receives input from an untrusted source; and replacing, at runtime of the program, the instance of the function with an instrumented version of the function that includes a marking function to indicate an output of the instrumented version of the function is tainted by the input received from the untrusted source. Additionally, instance instrumentation can be provided by identifying a second instance of the function in the program that does not receive input from the untrusted source; and leaving, at runtime of the program, the second instance of the function alone, wherein the second instance of the function is not replaced with the instrumented version of the function.

Abstract: A method for identifying design rule checking (DRC) violation types within an integrated circuit (IC) chip design includes receiving an IC chip design layout, and performing a DRC process on the IC chip design layout to identify DRC violations. Further, the method includes generating clustered heatmaps from heatmaps generated from the DRC violations. The method further includes identifying a first DRC violation type and a corresponding first cell pair within the IC chip design layout by analyzing the clustered heatmaps with a diagnostic model.

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Abstract: A method includes acquiring timing analysis data associated with a cell and activity data of one or more inputs of the cell, determining a glitch toggle rate for an output of the cell based on the activity data of the one or more inputs of the cell and the timing analysis data, and estimating a glitch power based on at least the glitch toggle rate.

Abstract: A method includes operating a digital simulator to mimic loading effects of digital circuit blocks of a circuit design on analog circuit blocks of the circuit design. The digital simulator sets a current signal timing and a current level value at an analog/digital boundary between the digital circuit aspects and the analog circuit aspects. The analog simulator is operated to apply the current signal timing and the current level value to simulate the analog circuit blocks.

Abstract: A memory transparent in-system built-in self-test may include performing in-system testing on subsets of memory cells over one or more test intervals of one or more test sessions. A test interval may include copying contents of a subset of memory cells to a register(s), writing test data (e.g., a segment of a pattern) to the subset of memory cells, reading back contents of the subset of memory cells, and restoring the content from the register(s) to the subset of memory cells. In-system testing may be performed on overlapping sets of memory cells. In-system testing may be performed on successive subsets of memory cells within a row (i.e., fast column addressing) and/or within a column (fast column addressing). In-system testing may be performed on sets of m blocks of memory cells during respective test intervals. The number of m blocks tested per interval may be configurable/selectable.

Abstract: A system for serializing data includes, in part, serialization circuitry configured to convert input data provided through parallel input streams into a lesser number of parallel output streams. The input data is converted through sampling based on a set of clock signals that are phase-offset. The system further includes a pre-driver circuit having combinational logic including a first multiplexer. The first multiplexer is configured to generate an output of the pre-driver circuit through combining the converted input data such that the number of parallel output streams is reduced. The system further includes a driver circuit configured to generate, using the output of the pre-driver circuit, a final output stream corresponding to the input data in serial format. The driver circuit is integrated with a second multiplexer, with the output of the pre-driver circuit operating as both control input and data input to the second multiplexer.