Abstract: Various embodiments of a method and apparatus for determining parametric timing yield and bottlenecks are disclosed which take into account correlation between electrical circuit paths through common timing arcs of an integrated circuit chip under design. Monte Carlo samples of timing arc delays are generated and used in computing timing yield and identify yield bottlenecks.

Abstract: A method of using on-chip circuitry to test a memory of a chip is provided. The method including, in a capture stage, receiving, at a first n-bit compression structure including n first stage latches corresponding to each bit of the first n-bit compression structure, a value at each respective first stage latch for each of n memory addresses of the memory, such that each respective first stage latch receives a respective value from a memory address of the memory, n being an integer greater than one, and in the capture stage, passing the values from each respective first stage latch through compression logic of the first n-bit compression structure to output a single compressed address value, providing the single compressed address value to a second stage latch of the first n-bit compression structure.

Abstract: A system and method for evaluating optimization of a hardware engine are described herein. In an example embodiment, a first operation of a desired application is performed using one or more hardware resources each associated with one or more task graphs of a plurality of task graphs. A first result is recorded from a first simulation based on a first task graph of the plurality of task graphs implemented using a first configuration of a first hardware resource associated with the first task graph. A second result is recorded from a second simulation based on a second task graph of the plurality of task graphs implemented using a second configuration of a second hardware resource associated with the second task graph. An interface is generated based on the first result and the second result for rendering by a display device.

Abstract: Embodiments relate to reading signals from a stimulus file produced by an emulator into a data store. A method includes executing, by a set of one or more worker processes, reading tasks. Each reading task is executable independent of other reading tasks. Each reading task includes reading a time slice of a signal from a stimulus file produced by a hardware emulator, and pushing a partial waveform corresponding to the time slice to a data store. The partial waveform includes a head and a tail that each has a smaller data size than an entirety of the partial waveform. The method further includes executing stitching tasks. The stitching tasks include pulling the heads and tails of the partial waveform from the data store, modifying the heads and tails to indicate a temporal order of the partial waveforms, and pushing the modified heads and tails back to the data store.

Abstract: Tracking circuitry for a memory device is disclosed. The tracking circuitry includes an inverter, a level shifter, delay circuitry, and a logic gate. The inverter is configured to receive a first clock signal and generate an inverted clock signal. The level shifter is configured to receive the first clock signal and the inverted clock signal and generate a level shifted clock signal. The delay circuitry is configured to receive the level shifted clock signal and generate an inverted level shifted clock signal. The logic gate comprises a first input configured to receive the first clock signal and a second input configured to receive the inverted level shifted clock signal. The logic gate is configured to generate a second clock signal based on the first clock signal and the inverted level shifted clock signal.

Abstract: Disclosed is a configuration to store metadata using an error correction code (ECC). The configuration receives at an ECC encoder of a memory controller, write data and an N-bit metadata, N comprising an integer greater than 0. The configuration generates a meta symbol using the N-bit metadata and creates an enhanced write data, the enhanced write data comprising the write data and the meta symbol generated by the N-bit metadata. The configuration encodes the enhanced write data and meta symbol to generate a parity. It deletes the meta symbol to generate an output, the output comprising an enhanced codeword and writes the enhanced codeword to a memory.

Abstract: Methods for diagnosing faults in memory periphery circuitry, computer readable media, and a test device for the same are provided. In one example, method is provided that includes receiving, at a test device, a first test syndrome from a memory device, the first test syndrome corresponds to a first test process executed by the memory device, wherein the memory device comprises a memory array and peripheral circuitry, and wherein the first test process is associated with a first circuit element of the peripheral circuitry; determining, by a processing device of the test device, a first fault associated with the first circuit element based on the first test syndrome; and diagnosing, by the processing device, the first fault to determine positional information of the first fault, the positional information is associated with the first circuit element.

Abstract: A method includes: receiving value changes corresponding to timestamped logic value changes in recorded signals from a verification run of an integrated circuit (IC) design; generating recorded logic vectors from the value changes, each of the recorded logic vectors being associated with a corresponding signal identifier, each of the recorded logic vectors including a recorded logic values over a window of consecutive clock cycles computed from one or more value changes associated with the corresponding signal identifier and having timestamps within the window of consecutive clock cycles; determining, by a processor, inferred logic vectors including inferred logic values corresponding to signals output by cells of the IC design based on propagating the recorded logic values of the recorded logic vectors through the cells; and computing per-cycle power characteristics of the IC design based on the recorded logic vectors and the inferred logic vectors.

Abstract: A voltage driver for supplying a supply voltage includes multiple PMOS transistors, multiple NMOS transistors, a pad, impedance divider circuits, NMOS clampers, and PMOS clampers. A maximum of the supply voltage is N times a maximum of the drain-source voltage of each transistor. The pad is configured to receive a voltage signal for dynamically controlling gates of a subset of the NMOS transistors and a subset of the PMOS transistors. The impedance divider circuits are configured to generate limited voltage signals, each of which is a fraction of voltage between the pad and supply voltage or between the pad and ground. The NMOS clampers and PMOS clampers configured to receive reference voltages and limited voltage signals to generate output, which is in turn input into gate terminals of the subset of NMOS or PMOS transistors.

Abstract: A method includes instantiating a first plurality of rows in a first region of a fabric. The first region has a height corresponding to a sum of heights of the first plurality of rows. The method also includes instantiating a second plurality of rows in a second region of the fabric. The second region is horizontally adjacent to the first region in the fabric. The second region has a height corresponding to a sum of heights of the second plurality of rows. The method further includes determining whether a row of the first plurality of rows is misaligned with a row of the second plurality of rows and adding a transition region between the row of the first plurality of rows and the row of the second plurality of rows in response.

Abstract: A method of forming a complementary field effect transistor (CFET) is provided. The method includes adding a blocking material to a vertical channel of the CFET having an epitaxial growth, the blocking material being located below and in contact with a lower portion of the growth, adding an insulating material to an open area within the vertical channel to surround a portion of the epitaxial growth, performing an etch to (i) remove a portion of the insulating material, (ii) expose a contact surface of the epitaxial growth and (iii) provide a vertical opening within the vertical channel, the etch leaving a portion of the blocking material, and filling in the vertical opening with a conductive material, the conductive material reaching the exposed contact surface of the epitaxial growth, the blocking material remaining below the conductive material to prevent contact between the conductive material and a silicon substrate below the growth.

Abstract: On-the-fly multi-bit flip-flop (MBFF) generation is provided by selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks; identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected flip-flop blocks; and generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.

Abstract: A semiconductor memory includes, in part, M×N select transistors disposed along M rows and N columns, where M and N are integers greater than or equal to 2. The memory further includes, in part, a first set of M wells each configured to be biased independently of the remaining M?1 wells. Each well has formed therein N of the select transistors each having a source/drain terminal coupled to the same bitline corresponding to a different one of M bitlines of the memory. The memory further includes, in part, M×N anti-fuses. Each anti-fuse is associated and forms a bitcell with a corresponding one of the M×N select transistors.

Abstract: A differential multiplexer includes a number of input stages. Each stage includes, in part, first and second transistor receiving an input signal and the inverse of the input signal, a biasing circuit supplying a bias to the gate terminal of the first and second transistors, a current source coupled between a source terminal of the first and second transistors and a ground terminal, a first switch coupling a drain terminal of the first transistor to a first terminal of a first resistor having a second terminal coupled to a supply voltage, a second switch coupling a drain terminal of the second transistor to a first terminal of a second resistor having second terminal coupled to the supply voltage, a third switch coupling the drain terminal of the first transistor to the supply voltage, and a fourth switch coupling the drain terminal of the second transistor to the supply voltage.

Abstract: A system determines physical design information along a logic hierarchy of a circuit design. The system accesses physical design metrics associated with different parts of a physical design of a circuit. The system accesses a logic design of the circuit comprising a hierarchy of logic blocks. The system determines the physical design metrics associated with one or more logic blocks of the hierarchy of the logic design based on a relation between the physical design and the logic design. The system configures a user interface to display the hierarchy of the logic design of the circuit along with the physical design metrics associated with the one or more logic blocks of the hierarchy. The system sends the configured user interface for display.

Abstract: A circuit provides fail safe protection of an input/output (I/O) circuit of a chip. The I/O circuit comprises an I/O pad connected to one or more other chips via an I/O bus. The circuit comprise a supply and failsafe detector component. The supply and failsafe detector component generates an I/O supply output signal. The I/O supply output signal has a low voltage value when the I/O supply voltage of the chip is below a medium voltage level and the I/O supply output signal having a high voltage value when the I/O supply voltage of the chip is above the medium voltage level. The medium voltage is above a threshold voltage of the transistor of the I/O circuit and below the high voltage value. The circuit uses the I/O supply output signal to provide a reference voltage as input to the transistor of the I/O circuit.

Abstract: A level shifter circuit includes a level shifter configured to receive a first clock signal associated with a first power level and generate a second clock signal associated with a second power level, wherein the second power level is greater than the first power level. The level shifter circuit further includes an input clock buffer having a first input, wherein the first input comprises the second clock signal from the level shifter, and a second input coupled in parallel to the first input, wherein the second input includes the first clock signal.

Abstract: Some aspects of this disclosure are directed to implementing hardware-based obfuscation of digital data. For example, some aspects of this disclosure relate to a method, including performing a capture operation that loads a plurality of primary input (PI) bits into corresponding shift registers of a plurality of test data registers (TDRs) disposed on one or more digital semiconductor devices and configured to store a plurality of secret information bits. The method further includes performing a sequence of shift operations on the plurality of TDRs to obtain a plurality of output bits. The method further includes applying, by an authenticating processor, a derivation function on the plurality of output bits to extract the plurality of secret information bits thereby authenticating the one or more digital semiconductor devices.

Abstract: A single-ended to a differential signal converter (converter) includes, in part, first, second, and third inverting elements, each having a first size, and coupled in series to form a chain of inverting elements. The converter further includes a fourth inverting element of a second size and coupled to the input of the first inverting element, a fifth inverting element of a third size and coupled to an output terminal of the first inverting element, a sixth inverting element of the third size and coupled to an output of the second inverting element, and a seventh inverting element of the second size and coupled to the output of the third inverting element. The outputs of the fourth and sixth inverting elements form a first one of the differential signals. The outputs of the fifth and seventh inverting elements form a second one of the differential signals.

Abstract: A circuit includes a clock generator, a frequency divider, and a first biasing circuit. The clock generator generates a clock signal of a first frequency. The frequency divider includes a first pair of cross coupled transistors. The frequency divider produces the clock signal of a second frequency. The first biasing circuit is coupled with the first pair of cross coupled transistors of the frequency divider. The first biasing circuit is adapted to enable a change in a transconductance of the first pair of cross coupled transistors to stabilize a phase angle between the clock signal at the first frequency and the clock signal at the second frequency.