Abstract: A circuit is provided. The circuit includes a first master stage, a second master stage, a first slave stage, a first slave stage, and a second slave stage. The first master stage includes a data input line. The second master stage includes an inverse data input line. The first slave stage is coupled to an output of the first master stage. The second slave stage is coupled to an output of the second master stage. The first slave stage generates an output signal during a rising edge of a clock cycle. The second slave stage generates an inverted output signal during the rising edge of the clock cycle. The output signal and the inverted output signal are available concurrently.

Abstract: In certain embodiments, a method includes the following steps. A layout used in a lithographic mask development process is accessed. For example, the layout may be the layout of the mask itself, or it may be the layout of the resulting printed pattern on the wafer. The layout includes a number of disjoint shapes. Skeleton representations for at least some of the disjoint shapes in the layout are determined. The skeleton representation of an individual shape has elements of two or more nodes connected by edges. It also includes size parameters for at least some of the elements. The skeleton representations of the shapes are used in the mask development process.

Abstract: For each defect in a set of defects, the defect may be associated with a defect attribute constructed from a set of computer-aided design (CAD) identifiers associated with polygons in an integrated circuit (IC) design that overlap with a defect area of the defect. Next, the set of defects may be segregated into defect groups based on the associated defect attributes. The defect groups may be used to perform additional processing on the set of defects.

Abstract: Test packets may be received at a design under test (DUT) from an automated test equipment (ATE) over a serializer/deserializer (SERDES) connection between the ATE and the DUT. The test packets may include test pattern data to test the DUT. The test pattern data may be applied to the DUT using a set of scan chains and test response data corresponding to the test pattern data may be obtained. The test response data may be received by a circuit in the DUT at irregular time intervals. Response packets may be sent to the ATE by the circuit in the DUT at regular time intervals, where the response packets may include a portion of the test response data (which may be encoded using an encoding technique), and where the response packets may be sent to ATE over the SERDES connection.

Abstract: An equalizer circuit includes: a main stage circuit including: a main stage differential pair; and a main stage degeneration resistance; a replica stage circuit including: a replica stage differential pair matching the main stage differential pair; and a replica stage degeneration resistance matching the main stage degeneration resistance and disconnected from the replica stage differential pair; equalizer inputs connected to: gate electrodes of the main stage differential pair; and gate electrodes of the replica stage differential pair; and equalizer outputs connected to: a main stage positive output and a main stage negative output connected to drain electrodes of the main stage differential pair; and a replica stage positive output and a replica stage negative output connected to drain electrodes of the replica stage differential pair, the replica stage positive output connected to the main stage negative output and the replica stage negative output connected to the main stage positive output.

Abstract: A method includes storing a base model generated using base data and receiving training data generated by compiling circuit designs. The method also includes generating, using the training data, a tuned model and generating, using the training data and the base data, a hybrid model. The method further includes receiving a selected cost function and biasing the base model, the tuned model, and the hybrid model using the selected cost function.

Abstract: Hardware description language (HDL) code for an integrated circuit (IC) design may be parsed to obtain an IC design parse tree. A transformation pattern may include a first pattern and a second pattern. The transformation pattern may be parsed to obtain a transformation pattern parse tree. The IC design parse tree and the transformation pattern parse tree may be used to identify a portion of the HDL code that matches the first pattern. The identified portion of the HDL code may be transformed based on the second pattern to obtain a transformed portion of the HDL code. The portion of the HDL code may be replaced by the transformed portion of the HDL code.

Abstract: A device includes a memory, a plurality of registers, a multiplexer/demultiplexer circuit, and a controller circuit. The memory stores a plurality of pages of pointers and a table of commands. The plurality of registers store information about a plurality of target devices. The multiplexer/demultiplexer circuit selects (i) information from a register of the plurality of registers based on a request received from a target device of the plurality of target devices, (ii) a page from the plurality of pages based on the selected information, and (iii) a pointer from the selected page based on the selected information. The controller circuit executes a command from the table of commands based on the selected pointer.

Abstract: A system and a method are disclosed for emulating a design of an electronic circuit. One or more field programmable gate array (FPGA) overlays are programmed to implement a first set of logic elements of the design of the electronic circuit. A second set of logic elements of the design of the electronic circuit is implemented in one or more FPGAs. The FPGA overlays implementing the first set of logic elements and the FPGAs implementing the second set of logic elements are interconnected to each other. The design of the electronic circuit is then tested using the interconnected FPGA overlays and the FPGAs.

Abstract: The present disclosure relates to a chip design layout process. More specifically, the present disclosure is directed to an incremental routing-based pin assignment technique. One example method generally includes: performing routing and pin assignment for a chip design layout, one or more objects of the chip design layout being associated with a routing engine and a pin assignment engine stored in memory; detecting a change associated with the one or more objects of the chip design layout; updating, via one or more processors, at least one of the routing engine or the pin assignment engine stored in the memory in response to the detected change and based on the association between the one or more objects and the routing engine or pin assignment engine; and performing another routing and pin assignment based on the updated at least one of the routing engine or the pin assignment engine.

Abstract: The present disclosure relates to improved electronic structures for propagating logic states between superconducting digital logic gates using a three-junction interferometer in a receiver circuit to reduce reflecting signals that otherwise result in distortions in the signals being transmitted between the gates. Other improved electronic structures comprise passive transmission lines (PTLs) with transmission line matching circuitry that has previously been avoided. The matching circuitry minimizes generation and propagation of spurious pulses emitted by Josephson junctions used in the digital logic gates.

Abstract: Embodiments herein describe a techniques for identifying a first combinational cell 210 in a design for an integrated circuit, identifying a plurality of candidate combinational cells 205 to combine with the first combinational cell using a first criterion. The techniques also include combining the first combinational cell with at least one of the plurality of candidate combinational cells to form a multi-bit (MB) combinational cell 100. Upon determining the MB combinational cell satisfies a performance threshold, the first combinational cell and the at least one of the plurality of candidate combinational cells are replaced with the MB combinational cell in the design.

Abstract: A method includes: receiving value changes corresponding to timestamped logic value changes in recorded signals from a verification run of an integrated circuit (IC) design; generating recorded logic vectors from the value changes, each of the recorded logic vectors being associated with a corresponding signal identifier, each of the recorded logic vectors including a recorded logic values over a window of consecutive clock cycles computed from one or more value changes associated with the corresponding signal identifier and having timestamps within the window of consecutive clock cycles; determining, by a processor, inferred logic vectors including inferred logic values corresponding to signals output by cells of the IC design based on propagating the recorded logic values of the recorded logic vectors through the cells; and computing per-cycle power characteristics of the IC design based on the recorded logic vectors and the inferred logic vectors.

Abstract: A method includes tracing from an observation point in a circuit to an input of the circuit to produce a cone of influence that includes a plurality of components of the circuit. The plurality of components is connected at a plurality of nodes in the cone of influence and the plurality of components includes a plurality of logic elements. The method also includes, for each node of the plurality of nodes, determining an observability probability that a logical high or low value at a corresponding node propagates to the observation point. The method further includes determining a weighted soft error probability for each logic element of the plurality of logic elements and determining a weighed soft error failure mode distribution for the cone of influence.

Abstract: A system and method for characterizing a memory instance. Characterizing a memory instance includes obtaining a memory instance comprising a plurality of leaf cells. Each of the plurality of leaf cells comprises components. First channel connected components from the components within each of the plurality of leaf cells are determined, and a first super leaf cell is generated by combining a first two or more leaf cells of the plurality of leaf cells based on the first channel connected components. Further, an updated memory instance is generated based on the first super leaf cell, and a timing model is determined for the updated memory instance.

Abstract: A method of determining a clock tree for a circuit includes, in part, generating a multitude of symmetric clock configurations characterized by a multitude of columns and a multitude of rows. For each symmetric clock configuration, the method further includes, in part, selecting positions of a multitude of tap points defined by a multitude of end points of the multitude of rows, estimating a first cost from a tree root to each of the first multitude of tap points, estimating a second cost from the multitude of tap points to a multitude of clock sinks associated with the multitude of tap points, and determining the symmetric clock configuration cost in accordance with the first cost and the second cost.

Abstract: In certain embodiments, a method includes the following steps. An engineering change order (ECO) is for fixing a violation of a target constraint on a target netlist of an integrated circuit. A constraint on a related netlist of the integrated circuit is identified. The identified constraint is adversely affected by fixing the violation of the target constraint. A processor concurrently modifies the target netlist to fix the violation of the target constraint and modifies the related netlist to prevent violation of the adversely affected constraint.

Abstract: Certain aspects are directed to apparatus and techniques for estimating parasitic information associated with routing of a design using a pre-route version of the design. One example method generally includes determining one or more output features using a machine learning model based on a pre-route version of a design of an integrated circuit, where the one or more output features include a density map providing an estimate of a density of elements associated with a routed version of the design. The method also includes estimating parasitic information associated with the design based on the one or more output features, and outputting the parasitic information.

Abstract: The independent claims of the present disclosure signify a concise description of embodiments. An electronic structure based on complementary-field effect transistor (CFET) architecture is disclosed. The electronic structure comprises an n-channel metal-oxide-semiconductior (NMOS) gate-all-around (GAA) channel in a first layer, and p-channel metal-oxide-semiconductor (PMOS) GAA channel in a second layer. The PMOS GAA channel is wider compared to the NMOS GAA channel. The first layer is above the second layer and separated by a dielectric layer.

Abstract: When designing circuits to meet certain constraint requirements, it is challenging to determine whether a given circuit design will meet the constraints. A designer at an early stage of the circuit design (e.g., synthesis or placement) may have limited information to rely on in order to determine whether the eventual circuit, or some design variation thereof, will satisfy those constraints without fully designing the circuit. The approaches described herein use a machine learning (ML) model to predict, based on features of partial circuit designs at early stages of the design flow, whether the full circuit is likely to meet the constraints. Additionally, the disclosed approaches allow for the ranking of various circuit designs or design implementations to determine best candidates to proceed with the full design.