Abstract: Techniques and systems for capturing and using routing intent in an integrated circuit (IC) design are described. Some embodiments use a graphical user interface (GUI) to capture routing intent for a net, wherein the routing intent includes a set of circuit objects associated with the net, a routing pattern, and optionally a set of user-provided attribute values. Next, the embodiments provide the routing intent to a router, wherein the router uses the routing intent to route the net.

Abstract: An application service request is parsed to identify an application service request parameter of the application service request. The application service request parameter is altered. The application service request is reconstructed to include the altered application service request parameter. The behavior of the application is analyzed while executing the reconstructed application service request to detect a security vulnerability. The detection of the security vulnerability is verified to eliminate false positives.

Abstract: A system is disclosed that includes a memory and a processor to perform operations, including analyzing rail voltage drop for a full-chip to identify an IR drop violation in a block design of the full-chip. The operations include performing a block-level rail voltage drop analysis for the block design and generating a revised block design corresponding to the block design in which the IR drop violation is identified. The operations include performing a block-level rail voltage drop analysis on the revised block design to verify that the IR drop violation is fixed and integrating the revised block design into the full-chip to replace the block design upon verifying that the IR drop violation is fixed. The operations include performing the rail voltage drop analysis for the full-chip comprising the revised block design.

Abstract: An example is a method. A design of an integrated circuit is loaded onto an emulation system and is emulated by the emulation system. A sequence of frames is captured, by the emulation system, from the emulation. The sequence of frames includes frame intervals, and each frame interval includes a full frame and a delta primary frame subsequent to the full frame. The full frame is captured at a respective sample time, and the full frame includes signals of the design or a change of the signals relative to a respective sample time of the full frame of a previous frame interval. The delta primary frame is captured at a respective sample time, and the delta primary frame includes a change of a subset of the signals relative to a respective sample time of a previous frame of the respective frame interval. The sequence of frames is stored to memory.

Abstract: Computer-aided methods for simulating confined nanodevices are disclosed. In example implementations, atomic-scale model of the nanodevices are generated so that dimensions and materials are specified. Then, band structures which comprise wave functions and Eigen energies are calculated using First Principles Methods (FPM). Effective mass modeled which comprise wave functions and Eigen energies are generated. After that, spatial wave functions of the calculated FPM band structures are mapped to the generated effective mass band structures wave functions by considering global behavior. In response to the mapping, generated effective mass models are fitted to calculated FPM energies so that approximate electronic band structures of the confined nanodevices are modeled. Computer programs for carrying out the methods, data media and computer systems are also disclosed.

Abstract: A system including a user interface, a memory, and a processor configured to perform operations including receiving memory scrambling information including address scrambling information and data scrambling information, and associating one or more address bus bits of a plurality of address bus bits with an address grouping of a plurality of address groupings based on the address scrambling information is disclosed. In an embodiment, the address grouping corresponds to at least one address segment of a plurality of address segments. The operations include determining an error correction code for the at least one address segment that includes one or more address check bits. The operations include generating a physical layout of memory components based on the memory scrambling information. The memory components include at least one of the plurality of address bus bits, and the one or more address check bits.

Abstract: A memory bypass circuit for a memory device comprises: a word line disable circuit; a read and write activation circuit; an internal clock generator; and a write data input circuit. The word line disable circuit is coupled to a word line of the memory device for disabling a write function to the word line. The read and write activation circuit is coupled to the memory device for reading and writing of input data. The internal clock generator is coupled to the word line disable circuit and the read/write activation circuit. The write data input circuit is coupled to a write driver of the memory device for providing write data.

Abstract: In one aspect, a fault injection environment and a formal property verification environment are combined in a single integrated flow that allows the user to go back and forth between the two tasks. A system that unifies formal property verification and fault injection includes user interfaces that support the unified use model. In one approach, the FPV tool is the master and its user interface is the primary interface for the user to set up, run and debug faults as well as checkers. This interface allows the user to interactively select the FPV properties and/or the faults to be used for fault analysis. The user interface may provide a view of the faults, for example by listing faults or summarizing faults by class, type, etc.

Abstract: Techniques and systems for optimizing a logic network are described. Some embodiments automatically identify scenarios where Boolean methods are best driven by truth tables, binary decision diagrams (BDDs) or satisfiability (SAT). Some embodiments use circuit partitioning techniques that are based on hash-tables and topological sorting, and that are capable of grouping nodes with high simplification likelihood and still are able to efficiently scale to large circuits. Some embodiments feature a generalized resubstitution framework based on computing, and implementing, the Boolean difference between two nodes. Some embodiments include enhancements to (i) gradient-based and-inverter-graph (AIG) optimization, (ii) heterogeneous elimination for kerneling, and (iii) revisitation of maximum set of permissible functions (MSPF) computation with BDDs.

Abstract: The independent claims of this patent signify a concise description of embodiments. Multiple copies of the design or multiple designs are compiled into a single emulation module or prototype FPGA/sub-system to enable multiple concurrent users. The design is executed on the emulator or prototype with the main design clock always running. A debug transactor is attached to each copy of the design which connects to one software debugger per user. The improvement is especially important for long interactive debug sessions which often occur with embedded-software debug use models. This Abstract is not intended to limit the scope of the claims.

Abstract: A computer system records and recreates an interface navigation process performed by a user with a host system. The computer system observes the user's interactions with the various UI elements during an interface navigation process by using a browser extension for the browser application in which the user is performing the interface navigation process. The browser extension then stores information about the interactions the user is performing and the UI elements that they are being performed on. The browser extension sends the stored interactions to the computer system, which processes the interactions to generate steps of the interface navigation recording. In some embodiments, the computer system also identifies one or more UI elements present in the final UI state of the interface navigation process as “verifiers” that can be used to determine whether the recreation of the interface navigation process is successful.

Abstract: A computer implemented method for routing a multitude of conductors through a first routing area on a planar surface is presented. The method includes receiving data representing the first routing area bounded by two opposite longitudinal sides each having a different number of a multitude of first vertices. The first routing area includes one or more blockages. The method further includes determining one or more locations on at least one of the two opposite longitudinal sides for adding one or more second vertices, and decomposing the first routing area into a multitude of second routing areas each not including any of the one or more blockages. The method further includes performing a gateway model routing (GMR) of the multitude of conductors in each of the multitude of second routing areas using the multitude of first vertices and the added one or more second vertices.

Abstract: A calibrated lithographic model may be used to generate a lithographic model output based on an integrated circuit (IC) design layout. Next, at least a chemical parameter may be extracted from the lithographic model output. A calibrated defect rate model may then be used to predict a defect rate for the IC design layout based on the chemical parameter.

Abstract: Memory queues described herein use a single hardware and/or software architecture for a memory array. This memory array can be partitioned to be between one memory sub-array to implement a single memory queue and multiple memory sub-arrays to implement multiple memory queues. Various electrical signals provided by or provided to these multiple memory queues include addressing information to associate these various control signals with one or more of the multiple memory sub-arrays. In some situations, the memory queues can externally associate their corresponding read pointers to entries of one of their memory sub-arrays. In these situations, these memory queues can dynamically associate their read pointers to point to any entry from among their memory arrays and to read the data store therein starting from any random entry within their memory arrays.

Abstract: A fractional divider is described herein which effectively performs an integer division followed by phase shifting, pulse swallowing, and/or multiplexing to realize a fractional divisor. The fractional divider divides an input clocking signal by a first integer divisor in a first mode of operation or by a second integer divisor in a second mode of operation to provide a first phase of a divided digital signal. Thereafter, the fractional divider shifts the first phase of the divided digital signal to provide a second phase of the divided digital signal in the first and second modes of operation. Finally, the fractional divider synchronizes an output clocking signal to the first phase of the divided digital signal and the second phase of the divided digital signal in the first and second modes of operation.

Abstract: A clock generation and correction (CGC) circuit comprises a clock and data recovery (CDR) circuit, a start-of-frame (SOF) detector circuit, a counter, a digital logic circuit, a fractional-N phase locked loop (PLL), and an oscillator circuit. The CDR receives an input data signal and an internal clock signal and generates a recovered data signal. The SOF detector circuit generates a toggle signal based on a comparison of the recovered data signal to a predetermined data signal pattern. The counter generates a clock cycle count signal based on the toggle signal. The digital logic circuit generates a frequency adjustment signal based on an error in the frequency of the clock signal. The oscillator circuit generates an intermediate clock signal. The fractional-N PLL circuit receives the frequency adjustment signal and the intermediate clock signal and modifies the internal clock signal based on the frequency adjustment signal.

Abstract: A memory device having a wake-up protocol is disclosed. The memory device comprises a plurality of bitcells operative in a deep-sleep mode having corresponding bitline pairs coupled to the plurality of bitcells, a first PFET coupled between a core voltage supply and the plurality of bitcells configured to supply a core voltage to the plurality of bitcells, and a second PFET having a drain coupled to the plurality of bitcells, a source coupled to a gate of the first PFET, and a gate configured to receive a first wake signal to enable precharge of the plurality of bitcells.

Abstract: A layout versus schematic (LVS) tool identifies a detected mismatch between a first graph representing a circuit layout and a second graph representing a circuit schematic. The detected mismatch is a device or net represented by a first node in the first graph and a corresponding second node in the second graph. The LVS tool assigns a first value to the first node and to the second node. The LVS tool iterates through nodes in the first graph and nodes in the second graph to assign values based on the first value, according to a graph coloring algorithm, until reaching a third node of the first graph and a corresponding fourth node of the second graph that are assigned different values. The LVS tool generates an output identifying the third node and the fourth node as a root cause of the detected mismatch.

Abstract: A computerized system is disclosed. The computerized system may include one or more processors configured to perform the operations stored in a memory. The operations may include sorting a subset of a plurality of endpoints for communication during a communication frame first based on service interval time assigned to each endpoint and then resorting based on a concurrency score of each peripheral device corresponding to the subset of the plurality of endpoints. The operations may include determining available bandwidth and a number of packets to be communicated with the each endpoint of the subset of the plurality of endpoints. The operations may include generating a scheduling table that includes the number of packets and an order of communication of the packets to be communicated with the each endpoint of the subset of the plurality of endpoints.

Abstract: This disclosure describes a memory cell array with enhanced read sensing margin. The memory cell array includes a write port and a read port being connected through first and second data storage lines. The memory cell array further includes multiple word lines and bit lines arranged in rows and columns such that the read port is coupled to a read word line, a read bit line, and a virtual ground. The read port includes a first transistor coupled to at least the read bit line and the virtual ground, a second transistor coupled to at least the first data storage line and the first transistor, a third transistor coupled to at least the second data storage line and the read word line, and a fourth transistor coupled at least the first data storage line and the read word line.