Abstract: A search for a regular expression in a tree hierarchy, includes, in part, searching for a match to the regular expression in a first subtree defined by a first node name, recording information about the first subtree if there is no match, determining whether a second subtree defined by a second node name is identical to the first node, skipping search of the second subtree if the second subtree is determined to be identical and prefix equivalent, with respect to the regular expression, to the first subtree. The second subtree is determined to be prefix equivalent to the first subtree when for any string s, a first prefix defined by a concatenation of the first node name and the string s results in a match if and only if a second prefix defined by a concatenation of the second node name and the string s results in a match.

Abstract: Systems and methods for automatic test pattern generation (ATPG) for parametric faults are described. A model may be constructed to predict a measurement margin for an integrated circuit (IC) design based on a random sample of random variables. A set of failure events may be determined for the IC design using the model, where each failure event may correspond to a set of values of the random variables that is expected to cause a metric for the IC design to violate a threshold.

Abstract: A method of generating a mask used in fabrication of a semiconductor device includes, in part, selecting a source candidate, generating a process simulation model that includes a stochastic variance band model in response to the selected source candidate, performing a first optical proximity correction (OPC) on the data associated with the mask in response to the process simulation model, assessing one or more lithographic evaluation metrics in response to the OPC mask data, computing a cost in response to the assessed one or more lithographic evaluation metrics, and determining whether the computed cost satisfies a threshold condition. In response to the determination that the computed cost does not satisfy the threshold condition, a different source candidate may be selected.

Abstract: Seamless transitions between routing modes are provided via providing a cursor in association with a design layout; in response to receiving a follow-the-cursor (FTC) command at a first position in the design layout, create a first trace in the design layout where the cursor is displayed; in response to receiving a start command for point-to-point routing at a second position in the design layout: complete the first trace at the second position; and provide an indicator at the second position; in response to receiving an end command for point-to-point routing at a third position in the design layout: create a second trace in the design layout where the cursor is displayed; and create a third trace in the design layout, wherein the third trace is routed from the first trace to the second trace.

Abstract: A method for assigning connections between IO pad pins and connectors on an integrated circuit (IC) die. A pattern (300) including a physical layout of connectors (302) and pad pins (304) is associated with a mapping of connections between the connectors (302) and the pad pins (304). A processor (204) identifies instances (402, 404) of the pattern (300) within a design image (400) of an integrated circuit (IC) die using a machine learning model. The design image (400) includes a physical layout of connectors (414) and pad pins (416). For each identified instance (402, 404) of the pattern (300) within the design image (400), the mapping of connections is assigned to respective connectors (414) and pad pins (416) in the identified instance (402, 404).

Abstract: A system for clock calibration is described herein which comprises a serializer configured to convert an input data stream in parallel format to provide an out data stream in a serial format; a clock source configured to generate one or more clock signals; a first frequency divider configured to provide at least one divided clock signal of the one or more clock signals; a delay line configured to delay at least one divided clock signal; and a clock calibrator configured to control delay of the at least one divided clock signal at the delay line to adjust the one or more divided clock signals at a fixed relationship with respect to the one or more clock signals based on voltage and temperature variation.

Abstract: The independent claims of this patent signify a concise description of embodiments. Roughly described, a design team prioritizes polygons of a circuit design layout. This information is then encoded into a layout database that is passed to the manufacturing team for correction further processing toward tape-out. The priorities may be used by an engineer to disposition errors found in the layout. For example, a failure may be waived. In another embodiment, the priorities are used during hotspot fixing, a process where failed features are corrected. In hotspot fixing, the priority can be used to make correction tradeoffs in favor of the highest priority features. Priorities are set during the correction to favor fidelity of the higher priority features over the lower priority features. Each embodiment reduces cost, and in some cases, improve final device performance. This Abstract is not intended to limit the scope of the claims.

Abstract: Methods, storage mediums, and apparatuses for evaluating the reliability of Three-Dimensional (3D) Network-on-Chip (NoC) designs are described. The described embodiments provide a 3D NoC specific fault-injector tool which is able to model logic-level fault models of 3D NoC specific physical faults in 3D-NoC platform. These embodiments automate the whole process of static and dynamic fault injection base on the user preference and reports the specific reliability metrics for 3D NoC platform as a single tool. The described embodiments can be used for the reliability evaluation and effectiveness of fault-tolerant designs in any of the 3D-many core designs such as manycore systems in different ranges of application from embedded systems in cellphones to larger systems which can be used in next generation of autonomous cars or hypercube memory cells.

Abstract: Techniques for verification of integrated circuit design are disclosed. A design relating to an integrated circuit is received (102). The design includes a first parameterized element and a second parameterized element (104). The first parameterized element is identified as a do-not-care (DNC) element based on usage of the first parameterized element in the design (106). A plurality of models relating to the design are generated by a processing device (110). A first value of the first parameterized element is not varied during the generating, based on the identification of the first parameterized element as a DNC element (108). A second value of the second parameterized element is varied during the generating (108).

Abstract: A hybrid electronic system including an emulator side including a processor and a first clock, a simulated side including one or more models to simulate one or more prototypes and a second clock, a first interface to the emulator side, and a second interface to the simulated side is disclosed. The processor is configured to determine using the first interface a first amount of time corresponding to an amount of time advanced on the emulator side by the first clock. The processor is configured to determine using the second interface a second amount of time corresponding to an amount of time advanced on the simulated side by the second clock, and set a value of a clock frequency of the second clock based on an initial value of the clock frequency of the second clock and a ratio of the first amount of time to the second amount of time.

Abstract: A netlist may include a set of resistance components of an integrated circuit (IC) design, and may specify a length, a width, and a metal layer of each resistance component in the set of resistance components, and physical locations of circuit nodes connected to each resistance component in the set of resistance components. A process description may specify the resistivity and thickness of each metal layer in the IC design. For a resistance component in the set of resistance components, resistivity and thickness of the metal layer of the resistance component may be determined based on the process description, and an inductance component corresponding to the resistance component may be determined based on the length and the width of the resistance component, the resistivity and the thickness of the metal layer of the resistance component, and the physical locations of the circuit nodes connected to the resistance component.

Abstract: An electronic design automation tool includes an application program interface API which includes a set of parameters and procedures supporting atomistic scale modeling of electronic materials. The procedures include a procedure to execute first principles calculations, a procedure to process results from the first principles calculations to extract device scale parameters from the results, a procedure to determine whether the extracted device scale parameters lie within a specified range. The procedures also include a procedure to parameterize an input parameter of a first principles procedure, including a procedure to execute a set of DFT computations across an input parameter space to characterize sensitivity of one of the intermediate parameter and the output parameter. Also included is a procedure to execute a second set of DFT computations across a refined input parameter space. The procedures include a procedure that utilizes DFT computations to parameterize the force field computations.

Abstract: Techniques and systems for classifying non-detected faults (NDFs) in a formal verification test-bench are described. A sequential equivalence checking formulation can be constructed based on an integrated circuit (IC) design and a set of NDFs, wherein the set of NDFs do not falsify a first set of properties of the IC design, wherein said constructing the sequential equivalence checking formulation comprises creating a second set of properties based on the set of NDFs, wherein each property in the second set of properties corresponds to an NDF in the set of NDFs. A formal sequential equivalence checking tool can be used to prove the second set of properties in the sequential equivalence checking formulation. Next, for each property in the second set of properties that is disproven by the formal sequential equivalence checking tool, some embodiments can classify a corresponding NDF in the set of NDFs as an observable NDF.

Abstract: A structure for an integrated circuit is disclosed for storing data. The integrated circuit includes a memory cell array of bit cells configured in a static random access memory (SRAM) architecture. The memory cell array is coupled to wordlines arranged in rows that control operations such as Read and Write operations. To enhance the read sensing margin of the SRAM configuration, the read port of a bit cell may include a wordline that drives two transistors (e.g., a PMOS and an NMOS transistor) to reduce data-dependent current leakage from a read bitline. An additional weak transistor keeper configuration may be used in the integrated circuit to compensate for current leakage from the read bitline. For example, a weak NMOS keeper that includes a sense amplifier, an inverter, and an NMOS connected to supply voltage VDD provides a path between the read bitline and VDD through the weak NMOS keeper.

Abstract: A system and a method are disclosed for error correction during operations of a memory system. For example, during a read operation, the error correction includes a read retry determination to account for link errors that are detectable by cyclic redundancy check (CRC) but not correctable by error correction coding (ECC). Reducing the number of read retry operations performed may improve system performance by reducing the number of clock cycles spent on retry operations that could have otherwise been allocated for other system services (e.g., completing read and write operations). Additional CRC calculations and checks may be used to determine when to perform a retry in addition to existing CRC and ECC checks, reducing the number of potential retry operations and improving system performance.

Abstract: Aspects described herein relate to obtaining a mask pattern using a cost function gradient (CFG) generated from a Jacobian matrix generated from a perturbation look-up table (PLT). In an example method, a PLT is populated (108). Each table entry of the PLT is based on a respective perturbed intensity signal. The respective perturbed intensity signal is based on a simulated signal received at an image surface using a mask pattern having a perturbed element of the mask pattern. The mask pattern is for a design of an integrated circuit. A matrix is populated (110) using the PLT and a target intensity signal. The target intensity signal is based on a signal received at the image surface to form target features at the image surface. A CFG is defined (112) based on the matrix. An analysis is performed (114) on the mask pattern based on the CFG.

Abstract: A method includes capturing a photon emission microscope (PEM) image of an integrated circuit (IC), and identifying emission sites in the PEM image, where the emission sites are associated with a leakage current. A set of common nets is found that connects multiple emission sites using layout data and/or netlist data in computer-aided design (CAD) data. From the layout data and/or netlist data, a critical net is identified from the set of common nets connecting a threshold number of emission sites. The critical net is cross-mapped, by a processor, tip netlist data in the CAD data. A particular device is identified from the netlist data that has an output pin connected to the critical net. The particular device identified from the netlist data is cross-mapped, by a processor, to the layout data, wherein the critical net connects at least two devices at the identified emission sites including the particular device.

Abstract: A static random access memory (SRAM) system includes a plurality of SRAM storage cells, each of the plurality of SRAM storage cells coupled to a respective read bit line, and a dynamic keeper coupled to the read bit line. The dynamic keeper includes a first keeper to support a read operation at a first temperature range, and a second keeper to support the read operation at a second temperature range, and a temperature-sensitive control circuit to select the first keeper or the second keeper based on temperature.

Abstract: A defect map may be created by merging defects at locations on multiple dies that include copies of an integrated circuit (IC). Layout shapes or nets may be determined that overlap with the defects in the defect map. Next, connectivity between the layout shapes or nets may be determined. The defects may then be grouped into defect groups based on the connectivity between the layout shapes or nets, where each defect group comprises defects that overlap with layout shapes or nets that are electrically connected to each other.

Abstract: A computerized system is disclosed. The computerized system may include one or more processors configured to perform the operations stored in a memory. The operations may include receiving a first circuit design pattern including a DRC violation and generating a first pattern matrix based on the first circuit design pattern, and updating the first circuit design pattern, based on the first pattern matrix, to fix the DRC violation. The operations may also include determining a possibility of a DRC violation-free first circuit design pattern corresponding to the first pattern matrix, and generating a first target label specifying the fixability corresponding to the first pattern matrix based on the determined possibility of the DRC violation-free first circuit design pattern. The first pattern matrix and the first target label may be used as training data to train a machine-learning model to predict fixability of the DRC violation.