Abstract: A device includes a memory, a plurality of registers, a multiplexer/demultiplexer circuit, and a controller circuit. The memory stores a plurality of pages of pointers and a table of commands. The plurality of registers store information about a plurality of target devices. The multiplexer/demultiplexer circuit selects (i) information from a register of the plurality of registers based on a request received from a target device of the plurality of target devices, (ii) a page from the plurality of pages based on the selected information, and (iii) a pointer from the selected page based on the selected information. The controller circuit executes a command from the table of commands based on the selected pointer.

Abstract: A method includes storing a base model generated using base data and receiving training data generated by compiling circuit designs. The method also includes generating, using the training data, a tuned model and generating, using the training data and the base data, a hybrid model. The method further includes receiving a selected cost function and biasing the base model, the tuned model, and the hybrid model using the selected cost function.

Abstract: Hardware description language (HDL) code for an integrated circuit (IC) design may be parsed to obtain an IC design parse tree. A transformation pattern may include a first pattern and a second pattern. The transformation pattern may be parsed to obtain a transformation pattern parse tree. The IC design parse tree and the transformation pattern parse tree may be used to identify a portion of the HDL code that matches the first pattern. The identified portion of the HDL code may be transformed based on the second pattern to obtain a transformed portion of the HDL code. The portion of the HDL code may be replaced by the transformed portion of the HDL code.

Abstract: The present disclosure relates to improved electronic structures for propagating logic states between superconducting digital logic gates using a three-junction interferometer in a receiver circuit to reduce reflecting signals that otherwise result in distortions in the signals being transmitted between the gates. Other improved electronic structures comprise passive transmission lines (PTLs) with transmission line matching circuitry that has previously been avoided. The matching circuitry minimizes generation and propagation of spurious pulses emitted by Josephson junctions used in the digital logic gates.

Abstract: Embodiments herein describe a techniques for identifying a first combinational cell 210 in a design for an integrated circuit, identifying a plurality of candidate combinational cells 205 to combine with the first combinational cell using a first criterion. The techniques also include combining the first combinational cell with at least one of the plurality of candidate combinational cells to form a multi-bit (MB) combinational cell 100. Upon determining the MB combinational cell satisfies a performance threshold, the first combinational cell and the at least one of the plurality of candidate combinational cells are replaced with the MB combinational cell in the design.

Abstract: A method includes tracing from an observation point in a circuit to an input of the circuit to produce a cone of influence that includes a plurality of components of the circuit. The plurality of components is connected at a plurality of nodes in the cone of influence and the plurality of components includes a plurality of logic elements. The method also includes, for each node of the plurality of nodes, determining an observability probability that a logical high or low value at a corresponding node propagates to the observation point. The method further includes determining a weighted soft error probability for each logic element of the plurality of logic elements and determining a weighed soft error failure mode distribution for the cone of influence.

Abstract: A method of determining a clock tree for a circuit includes, in part, generating a multitude of symmetric clock configurations characterized by a multitude of columns and a multitude of rows. For each symmetric clock configuration, the method further includes, in part, selecting positions of a multitude of tap points defined by a multitude of end points of the multitude of rows, estimating a first cost from a tree root to each of the first multitude of tap points, estimating a second cost from the multitude of tap points to a multitude of clock sinks associated with the multitude of tap points, and determining the symmetric clock configuration cost in accordance with the first cost and the second cost.

Abstract: A system and method for characterizing a memory instance. Characterizing a memory instance includes obtaining a memory instance comprising a plurality of leaf cells. Each of the plurality of leaf cells comprises components. First channel connected components from the components within each of the plurality of leaf cells are determined, and a first super leaf cell is generated by combining a first two or more leaf cells of the plurality of leaf cells based on the first channel connected components. Further, an updated memory instance is generated based on the first super leaf cell, and a timing model is determined for the updated memory instance.

Abstract: The independent claims of the present disclosure signify a concise description of embodiments. An electronic structure based on complementary-field effect transistor (CFET) architecture is disclosed. The electronic structure comprises an n-channel metal-oxide-semiconductior (NMOS) gate-all-around (GAA) channel in a first layer, and p-channel metal-oxide-semiconductor (PMOS) GAA channel in a second layer. The PMOS GAA channel is wider compared to the NMOS GAA channel. The first layer is above the second layer and separated by a dielectric layer.

Abstract: In certain embodiments, a method includes the following steps. An engineering change order (ECO) is for fixing a violation of a target constraint on a target netlist of an integrated circuit. A constraint on a related netlist of the integrated circuit is identified. The identified constraint is adversely affected by fixing the violation of the target constraint. A processor concurrently modifies the target netlist to fix the violation of the target constraint and modifies the related netlist to prevent violation of the adversely affected constraint.

Abstract: Certain aspects are directed to apparatus and techniques for estimating parasitic information associated with routing of a design using a pre-route version of the design. One example method generally includes determining one or more output features using a machine learning model based on a pre-route version of a design of an integrated circuit, where the one or more output features include a density map providing an estimate of a density of elements associated with a routed version of the design. The method also includes estimating parasitic information associated with the design based on the one or more output features, and outputting the parasitic information.

Abstract: A method and system for guided power grid augmentation determines a minimum resistance path for cells within an integrated circuit (IC) design. The minimum resistance path traces a conducting wire connecting a pin of a cell to an IC tap within the IC design. A voltage drop value for each of the cells is determined so as to identify target cells having a voltage drop value that satisfies a voltage drop criteria. Polygons have defined size characteristics are defined around the minimum resistance paths of the target cells, and conductors, such as additional conductors, are generated within the defined polygons.

Abstract: Training data may be collected based on a set of test-case configurations for each integrated circuit (IC) design in a set of IC designs. The training data may include a set of features extracted from each IC design, and a count of test cycles required for achieving a target test coverage for each test-case configuration. A machine learning (ML) model may be trained using the training data to obtain a trained ML model. The trained ML model may be used to predict a set of ranked test-case configurations for a given IC design based on features extracted from the given IC design.

Abstract: This disclosure describes a system and method of automatically capturing source code and associated artifacts for static analysis. A method includes receiving a current state of a project that includes a set of files in a directory to be captured for analysis and a current capture status of individual files of the set of files, determining a plan including a sequence of actions in response to the current state of the project, and executing the sequence of actions to capture each of the set of files. The sequence of actions includes capturing buildable modules in the set of files with a build-capture based on a default build command and a buildless-capture based on module definition files.

Abstract: Clock multiplexer circuitry outputs one of a first or second clock signal. First selection circuitry is connected in series with first counter circuitry. The first selection circuitry and the first counter circuitry receive a first clock signal and a first selection signal. A first control signal is generated based on the first clock signal and the first selection signal. Second selection circuitry is connected in series with second counter circuitry. The second selection circuitry and the second counter circuitry receive a second clock signal and a second selection signal. A second control signal is generated based on the second clock signal and the second selection signal. The output circuitry is connected to the first counter circuitry and the second counter circuitry. The output circuitry outputs one of the first clock signal and the second clock signal based on the first control signal and the second control signal.

Abstract: A method comprises receiving an integrated circuit (IC) design file and determining, by one or more processors, dose information from the IC design file. The method further comprises determining, by the one or more processors, a mask vector file from the IC design file, and converting, by the one or more processors, the dose information to a vector file format. Further, the method comprises outputting the dose information in the vector file format and the mask vector file to a mask writer device.

Abstract: Methods and systems are described herein relate to automatic channel identification of high-bandwidth memory channels and subchannel generation. An HBM channel identification system may perform a sequence of operations to identify HBM channels within a netlist of an interposer: channel dimension prediction, channel bounding box prediction, channel orientation derivation, subchannel partition, and subchannel routing region creation. In one example, an HBM channel identification method includes identifying candidate nets within a netlist. A bounding box that includes one or more nets of the candidate nets is determined. Once the bounding box is determined, the orientation of the box is determined and used to determine a pattern of bumps within the bounding box. Finally, a subchannel is generated based on the pattern of bumps.

Abstract: Embodiments relate to a system and method for analyzing strongly connected components (SCCs) in a design of an integrated circuit. In one embodiment, a design of an integrated circuit is received, and a set of loops are identified in the received design. Based on the identified loops, one or more SCCs are determined. Each SCC includes multiple loops having shared paths. For instance, an SCC includes a first loop having a first set of nodes connected via a first set of paths and a second loop having a second set of nodes connected via a second set of paths, such that the first loop and the second loop have at least one path in common. The identified SCCs are then analyzed and presented to the user for consideration when reviewing the design of the integrated circuit.

Abstract: A method for debugging an electronic subsystem is disclosed. The method includes converting a first message in a first protocol format received at a first functional logical block of a plurality of functional logical blocks of an electronic subsystem into a second message in a second protocol format at the first functional logical block, wherein the second message includes a unique identifier (UID), and generating a first trace file corresponding to the first functional logical block, wherein the first trace file includes the UID. The method includes forwarding the second message from the first functional logical block to a second functional logical block. The method includes generating a second trace file corresponding to the second functional logical block, wherein the second trace file includes the UID, and performing an analysis on the first and the second functional logical blocks.

Abstract: An integrated circuit (IC) may include a memory device and a circuit coupled with the memory device. The circuit may precondition the memory device to sustain oscillations, initiate first oscillations in a first loop that includes the memory device, and initiate second oscillations in a second loop that does not include the memory device.