Abstract: A method includes receiving a design file for a circuit design and receiving a library that defines a cell that includes one or more inputs, a first combinational logic circuit element, a second combinational logic circuit element, a first output, and a second output. The method also includes replacing a plurality of circuit elements in the circuit design with the cell and compiling the circuit design after replacing the plurality of circuit elements with the cell. The first and second outputs of the cell in the compiled circuit design replace a plurality of outputs of the plurality of circuit elements.

Abstract: A multi-port, multi-mode Reed Solomon (RS) forward error correction system includes a plurality of data in lines, each associated with a data port. The system includes a syndrome block (SDM) that has a plurality of syndrome slices and a SDM switching logic. An input of a SDM slice couples with a data in line from the plurality of data in lines. The switching logic couples with an interface port width (IFW) line a mode line. The IFW line identifies a number of data in lines tied together and the mode line to identify a RS mode. A reformulated inversionless Berlekamp-Massey (RiBM) block has a plurality of RiBM slices and a RiBM switching logic. A Chien Forney (ChFr) block has a plurality of ChFr slices. An error evaluation magnitude (ErEval) block has a plurality of ErEval slices. A plurality of adders couple with an output of a corresponding ErEval slice.

Abstract: A method for forming ultra-high density integrated circuitry, such as for a 6T SRAM, for example, is provided. The method involves applying double patterning litho-etch litho-etch (LELE) and using a spacer process to shrink the critical dimension of features. To improve process margins, the method implements a double-patterning technique by modifying the layout and splitting cross-coupling straps into two colors (e.g., each color corresponds to a mask-etch process). In addition, a spacer process is implemented to shrink feature size and increase the metal-to-metal spacing between the two cross-coupling straps, in order to improve process margin and electrical performance. This is achieved by depositing a spacer layer over an opening in a hardmask, followed by spacer etch back. The opening is thus shrunk by the amount of spacer thickness. The strap-to-strap spacing may then be increased by twice the amount of spacer thickness.

Abstract: A circuit includes, in part, a first transistor receiving a first clock signal at its gate, a second transistor receiving a second clock signal at its gate, a first impedance coupled to the drain terminal of the first transistor, a second impedance coupled to the drain terminal of the second transistor, a current source coupled to the source terminals of the first and second transistors, a third transistor receiving a third clock signal at its gate, a fourth transistor receiving a fourth clock signal at its gate, a fifth transistor coupling the drain terminal of the third transistor to the second impedance in response to a first control signal, a sixth transistor coupling the drain terminal of the fourth transistor to the second impedance in response to a second control signal, and a first variable current source coupled to the source terminals of the third and fourth transistors.

Abstract: A method comprises receiving an integrated circuit (IC) chip design, and generating, by one or more processors and based on the IC chip design, dose information, a wafer image, and a wafer target. Further, the method comprises modifying, by the one or more processors, the dose information based on a comparison of the wafer image and the wafer target. Further, the method comprises outputting the modified dose information to a mask writing device.

Abstract: A method includes generating a plurality of vector sequences based on input signals of an electric circuit design and encoding the plurality of vector sequences. The method also includes clustering the plurality of encoded vector sequences into a plurality of clusters and selecting a set of encoded vector sequences from the plurality of clusters. The method further includes selecting a first set of vector sequences corresponding to the selected set of encoded vector sequences, selecting a second set of vector sequences from the plurality of vector sequences not in the first set of encoded vector sequences, and training, by a processing device, a machine learning model to predict power consumption using the first and second sets of vector sequences.

Abstract: A method for error correction comprises receiving data at a first device, and decoding, by decoder circuitry of the first device, the data. Decoding the data comprises determining a first error location within the data, and determining a first error magnitude within the data in parallel with determining the first error location. Decoding the data further comprises performing error correction to generate the decoded data based on the first error location and the first error magnitude. The method further comprises transmitting the decoded data to a second device.

Abstract: Glitch source identification and ranking is provided by: identifying a plurality of glitch sources in a circuit layout; back referencing the plurality of glitch sources to corresponding lines in a Resistor Transistor Logic (RTL) file defining the plurality of glitch sources; identifying, in the circuit layout, a plurality of glitch terminuses associated with the plurality of glitch sources; determining a plurality of glitch power consumption values associated with the plurality of glitch sources based on fanouts in the circuit layout extending from the plurality of glitch sources to the plurality of glitch terminuses; ranking, by a processor, the plurality of glitch sources based on corresponding glitch power consumption values of the plurality of glitch power consumption values corresponding to individual glitch sources of the plurality of glitch sources; and reporting the corresponding lines in the RTL file associated with the ranked plurality of glitch sources.

Abstract: A first set of critical dimension (CD) measurements of resist patterns created by a lithography process and a second set of CD measurements of water patterns created by an etch process may be obtained. A forward etch model and an inverse etch model may be calibrated together by reducing (1) a first prediction error between the second set of CD measurements and a first set of simulated CDs predicted by the forward etch model based on the resist patterns, a second prediction error between the first set of CD measurements and a second set of simulated CDs predicted by the inverse etch model based on the wafer patterns, and a matching error between the forward etch model and the inverse etch model.

Abstract: Aspects described herein relate to obtaining a mask pattern using a cost function gradient (CFG) generated from a Jacobian matrix generated from a perturbation look-up table (PLT). In an example method, a PLT is populated (108). Each table entry of the PLT is based on a respective perturbed intensity signal. The respective perturbed intensity signal is based on a simulated signal received at an image surface using a mask pattern having a perturbed element of the mask pattern. The mask pattern is for a design of an integrated circuit. A matrix is populated (110) using the PLT and a target intensity signal. The target intensity signal is based on a signal received at the image surface to form target features at the image surface. A CFG is defined (112) based on the matrix. An analysis is performed (114) on the mask pattern based on the CFG.

Abstract: A circuit can include a first sub-circuit, a second sub-circuit, and a third sub-circuit. The first sub-circuit can store a reset state or a set state, and can include a first Josephson junction (JJ), a second JJ, and a third JJ coupled in parallel using superconducting inductors. The first JJ, the second JJ, and the third JJ can be biased using a JJ-based current source. The second sub-circuit can switch the first sub-circuit to the set state in response to receiving a pulse. The third sub-circuit can switch the first sub-circuit to the reset state in response to receiving one or more pulses.

Abstract: Systems and methods for asynchronous communication are disclosed. For example, a method for asynchronous communication includes encoding, by a transmitter circuit and according to a first clock signal, a bit sequence by converting a one-bit in the bit sequence into a first sequence and a zero-bit in the bit sequence into a second sequence. A length of the first sequence and a length of the second sequence differ by at least three bits. The method also includes communicating, by the transmitter circuit, the first sequence and the second sequence to a receiver circuit that decodes the first sequence and the second sequence according to a second clock signal that is independent of the first clock signal.

Abstract: A method of generating a mask used in fabrication of a semiconductor device includes, in part, selecting a source candidate, generating a process simulation model that includes a defect rate in response to the selected source candidate, performing a first optical proximity correction (OPC) on the data associated with the mask in response to the process simulation model, assessing one or more lithographic evaluation metrics in response to the OPC mask data, computing a cost in response to the assessed one or more lithographic evaluation metrics, and determining whether the computed cost satisfies a threshold condition. In response to the determination that the computed cost does not satisfy the threshold condition, a different source candidate may be selected.

Abstract: A machine learning (ML) system is trained to predict the number of design rules violations of a circuit design that includes a multitude of Gcells. To achieve this, a netlist associated with the circuit design is placed by a place and route tool. A first list of features associated with the placed netlist is delivered to the ML system. A global route of the circuit design is performed by a global router. Next, a second list of features is delivered from the global router to the ML system. Thereafter, a detailed route of the circuit design is performed by a detailed router. A label associated with each Gcell in the circuit design is delivered to the ML system from the detailed route. The ML system is trained using the first and second list of features and the labels.

Abstract: Systems and methods for integrated circuit (IC) analysis using a multi-level data hierarchy implemented on a distributed compute and data infrastructure are described. An IC design may be represented using a set of storage areas, where each storage area may be stored in a contiguous block of storage and may correspond to a portion of the IC design. An analysis application may be executed on the IC design, where a subset of the set of storage areas that is used by the analysis application may be retrieved on-demand.

Abstract: Techniques for testing an integrated circuit (IC) are disclosed. A controller in the IC retrieves first testing data from a first memory in the IC. The controller transmits the first testing data to a first built-in self-test (BIST) core. The controller receives a response from the first BIST core, relating to a test at the first BIST core using the first testing data. The controller determines a status of the test relating to the IC based on the response.

Abstract: An input buffer circuit includes a tracking circuit that produces a tracking signal and an inverter including a cascade of low voltage switching devices coupled to an output of the tracking circuit. The tracking signal follows a first signal during a first time period and a second signal during a second time period. The tracking circuit is configured to reduce an input high voltage/input low voltage (VIH/VIL) spread.

Abstract: A system and method utilized to receive an integrated circuit (IC) design and generating a graph based on a plurality of sub-circuits of the IC design. Further, one or more candidate sub-circuits are determined from the plurality of sub-circuits based on the graph. Additionally, one or more sub-circuits are identified from the one or more candidate sub-circuits based on a number of transistors and a number of edges within each of the plurality of sub-circuits. An indication of the identified one or more sub-circuits is provided.

Abstract: A method for assigning connections between IO pad pins and connectors on an integrated circuit (IC) die. A pattern (300) including a physical layout of connectors (302) and pad pins (304) is associated with a mapping of connections between the connectors (302) and the pad pins (304). A processor (204) identifies instances (402, 404) of the pattern (300) within a design image (400) of an integrated circuit (IC) die using a machine learning model. The design image (400) includes a physical layout of connectors (414) and pad pins (416). For each identified instance (402, 404) of the pattern (300) within the design image (400), the mapping of connections is assigned to respective connectors (414) and pad pins (416) in the identified instance (402, 404).

Abstract: A system performs logic simulation of a circuit design specified using a hardware description language such as Verilog. The system performs constraint solving based on an expression specified in the specification of the circuit design. The system identifies required bits for each variable in the expression. The number of required bits is less than the number of bits specified in the variable declaration. The system performs bit-level constraint solving by performing a bit operation on the set of required bits and a simplified processing of the remaining bits of the variable. Since the original circuit design is preserved with the original bit-widths for simulation, those required bits are used on the fly internally during constraint solving. Furthermore, dynamic bit reductions on arithmetic operations are performed on the fly. The system improves computational efficiency by restricting bit operations to fewer bits of variables and operators of the expression.