Abstract: A self-tuning computing system and a method for self-tuning a computing system. The method includes measuring a current operation metric representing a current performance of the computing system; determining, based on the current operation metric and a target metric, at least one optimization scheme for improving the current operation metric, wherein the at least one optimization scheme includes at least a plurality of system knobs each having a respective optimal value; and setting each of the system knobs listed in the at least one determined optimization scheme to its respective optimal value.

Abstract: A clock recovery circuit may include a first circuit to produce an output signal that is a logical combination of an edge detection signal and a clock signal. At least some transitions in the edge detection signal may correspond to transitions in a set of data signals. The clock recovery circuit may also include a second circuit to average the output signal to produce a voltage, and a third circuit to add a variable delay to the clock signal based on the voltage.

Abstract: A set of attributes of software packages may be determined by analyzing a first set of software packages, where the set of attributes of software packages may be useful for uniquely identifying software packages in the first set of software packages. A heuristic may be created or a machine learning model may be trained that combines the set of attributes of software packages to uniquely identify software packages in the first set of software packages. The heuristic or the trained machine learning model may be used to categorize a second set of software packages, or determine relationships among a second set of software packages.

Abstract: A circuit is described that can include: a first register to store a first value that specifies a first subset of a set of scan chains, wherein the first subset of the set of scan chains includes scan cells that are desired to be masked; a second register to store a second value that specifies, in each shift cycle, a second subset of the set of scan chains, wherein the second subset of the set of scan chains includes scan cells that are desired to be masked; and a masking circuit to mask, in each shift cycle, scan cells in a third subset of the set of scan chains that is an intersection of the first subset of the set of scan chains and the second subset of the set of scan chains.

Abstract: Calibrating stochastic signals in compact modeling is provided by obtaining data of process variations in producing a resist mask; calibrating a continuous compact model of the resist mask based on the data; evaluating the continuous compact model against a stochastic compact model that is based on the data; choosing a functional description of an edge location distribution for the stochastic compact model; mapping image parameters from the evaluation to edge distribution parameters according to the functional description; determining an edge location range for the stochastic compact model based on scaled measurements from the image parameters; calibrating a threshold for the resist mask and updating parameters of the stochastic compact model to reduce a difference between the data and a modeled Line Edge Roughness (LER) value; and outputting the stochastic compact model.

Abstract: A method includes generating a first bitmap for a cell. The first bitmap is indicative of mapping constraints of the cell. The method also includes generating a second bitmap for a PSC filler cell. The second bitmap is indicative of the mapping constraints of the PSC filler cell. The method also includes a bitwise logical operation between a portion of the first bitmap and a respective portion of the second bitmap and determining a compatibility between the cell and the PSC filler cell based on at least a result of the bitwise logical operation.

Abstract: A system and method for providing convergence centric coverage for clock domain crossing (CDC) jitter in simulation is described. The method includes, in part, defining one or more design constraints associated with the circuit design, determining at least one group of converging signals associated with the circuit design using the one or more design constraints, applying a multitude of jitters to clock domain crossing (CDC) paths of the at least one group of converging signals, and storing the jitters in a jitter database.

Abstract: A hotspot detection system that classifies a set of hotspot training data into a plurality of hotspot clusters according to their topologies, where the hotspot clusters are associated with different hotspot topologies, and classifies a set of non-hotspot training data into a plurality of non-hotspot clusters according to their topologies, where the non-hotspot clusters are associated with different topologies. The system extracts topological and non-topological critical features from the hotspot clusters and centroids of the non-hotspot clusters. The system also creates a plurality of kernels configured to identify hotspots, where each kernel is constructed using the extracted critical features of the non-hotspot clusters and the extracted critical features from one of the hotspot clusters, and each kernel is configured to identify hotspot topologies different from hotspot topologies that the other kernels are configured to identify.

Abstract: Techniques for providing improved semiconductor yield learning are discussed herein. Some embodiments may include a yield learning vehicle (YLV), including a communication fabric and a plurality of circuit blocks connected with the communication fabric. The plurality of circuit blocks may include circuit blocks having different design window sizes, and may be configured to support different phases of a yield learning ramp up process. The YLV may further include a yield learning controller configured to control circuit block testing, and bypasses configured to partially or fully replicate the behavior of improperly functioning or untested circuit blocks. Some embodiments may include techniques for software implementation of the YLV, such as by invoking a computer to receive data representative of a design of the YLV, and based on the data representative of the design of the integrated circuit, causing the computer to generate data representative of YLV.

Abstract: A system and method for placement and simulation of a cell in proximity to a cell with a diffusion break is herein disclosed. According to one embodiment, an integrated circuit is designed to include a first cell that has a first edge and a second edge opposite the first edge. The first cell may also include a diffusion region that extends from the first edge to the second edge with a diffusion break separating the diffusion region. The diffusion break may be spaced away from the second edge by a distance that degrades a metric (e.g., a delay, a slew, dynamic power, or leakage) of a second cell placed next to the second edge beyond a threshold level.

Abstract: An EUV mask absorber formed on a semiconductor structure, includes, in part a sidewall forming am angle relative to a surface of the semiconductor structure that is less than 90 degrees. The sidewall includes a layer of reflective material. The semiconductor structure may include, in part, a multitude of layers. The semiconductor structure may be disposed on a glass substrate, a silicon substrate, or the like. The EUV mask absorber is adapted to shift a phase of the EUV light passing therethrough. The EUV mask absorber may further include, in part, a layer of Ruthenium near a bottom surface of the absorber structure. The EUV mask absorber may further includes, in part, a layer of reflective material near a top surface of the absorber structure. The EUV mask absorber may further include, in part, Tantalum Oxynitride.

Abstract: A method of determining the position of a first edge of a pattern in a mask used in fabricating an integrated circuit in which the first edge corresponds to a second edge associated with the pattern of a layout of the integrated circuit, includes, in part, dividing the edge into a multitude of segments, assigning a variable to each segment, applying a non-linear optimization algorithm to a current location of the first edge to determine an updated position of the first edge, determining a difference between the position of the second edge and a third edge corresponding to the updated position of the first edge and obtained by computer simulation of the mask pattern providing a model of the layout pattern when formed on a semiconductor wafer, and repeating the applying and the determining steps iteratively until the difference is smaller than a threshold value.

Abstract: A method of detecting a timing violation between a first sequential element and a second sequential element in a circuit design being emulated in a hardware emulation system includes, in part, determining a timing relationship between first and second clocks applied respectively to the first sequential element and the second sequential element, reconfiguring a combinational logic disposed between the first sequential element and the second sequential element as one or more buffers, setting a delay across the one or more buffers to one or more clock cycles of the hardware emulation system based on the timing relationship, reprogramming the first and second clocks in accordance with the delay, and detecting a timing violation if a change in an output of the first flip-flop is not stored in the second flip-flop within the delay.

Abstract: In one aspect, a method for displaying incompatible ports at the schematic design stage comprises the following. A schematic of a photonic integrated circuit is accessed. The schematic comprises a plurality of optical components that have ports, and the optical components are connected at their ports. A processor determines the structures of the ports. Typically, the structure of a port is determined by the cross-sectional shape and the material(s) of the port. The schematic of the photonic integrated circuit is displayed, with different visual indicators for ports with different structures. For example, ports with different structures may be represented by symbols of different colors, different outlines, different fill patterns or other types of non-textual visual indicators.

Abstract: To specifically identify faults within a semiconductor cell, a SPICE netlist associated with the semiconductor cell design is retrieved, and one or more transistor characteristics are identified within the SPICE netlist. An advanced cell-aware fault model is executed for the semiconductor cell, and results are returned for one or more fault test methods of the advanced cell-aware fault model for a cell of the semiconductor chip design. A method for identifying faults within the semiconductor cell continues by correlating one more faults detected as a result of the fault test methods with one or more transistor characteristics within the SPICE netlist, and a user interface is generated for identifying one or more faulty transistors within the semiconductor chip design.

Abstract: A method includes generating a netlist for a circuit design and predicting, by applying a first machine learning model to the netlist, a first compile time for the circuit design. The method also includes predicting, by applying a second machine learning model to the netlist, a first place and route strategy based on the first compile time. The method further includes adjusting a logic of the circuit design in accordance with the first place and route strategy.

Abstract: A system including a user interface, a memory, and a processor configured to perform operations stored in the memory is disclosed. The operations may include receiving an application specification including an application algorithm, and extracting from the application algorithm a first and a second node. The first node may include a first component of the application algorithm, and the second node may include a second component of the application algorithm that may be different from the first component. The operations may include analyzing execution dependency of the first node on the second node. The analyzing execution dependency may include analyzing computational requirements, bandwidth requirements, and input trigger requirements of the first node and the second node based on parallelism of available resources.

Abstract: A one-transistor (1T) one-time programmable (OTP) anti-fuse bitcell is provided. The 1T OTP anti-fuse bitcell includes a gate, a diffusion region including at least two sub-regions, and a gate oxide region located between the gate and the diffusion region, the gate oxide region including a thin gate oxide region and a thick gate oxide region.

Abstract: A method for representing a layout of an integrated circuit (IC) includes, in part, determining multiple regions of the IC layout based on one or more parameters, determining multiple areas associated with the multiple regions where each area has a characteristic of a region of the multiple regions, assigning a first set of values to locations of the IC layout outside the multiple areas, assigning a second set of values to locations of the IC layout within the multiple areas, and, in response to a determination that a location of the IC layout is in two or more overlapping areas of the multiple areas, determining a value to assign to the location in accordance with the values of the two or more overlapping areas. The method further includes generating data representative of the IC layout design in accordance with the first and second set of values, and the assigned value.

Abstract: A method of evaluating sampling sizes for circuit simulation comprises generating a plurality of coverage scenarios based on a defect universe, determining a coverage amount for each of the plurality of coverage scenarios, and associating the plurality of coverage scenarios with a plurality of bins based on the coverage amount for each of the plurality of coverage scenarios. The method further comprises sampling, with a first sampling size, each of the coverage scenarios to determine first sampled coverage scenarios, and determining an error value for each of the plurality of coverage scenarios based on the coverage amount of each of the plurality of coverage scenarios and a coverage amount of a respective one of the first sampled coverage scenarios.