Patents Assigned to Synopsys, Inc.
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Patent number: 11797735Abstract: A method of testing a product using confidence estimates is provided. The method includes identifying a set of candidate tests and estimating a respective confidence score for each candidate test, the confidence scores reflecting a level of confidence that the corresponding candidate tests will pass or fail when being performed on the product, the estimating including determining the respective confidence scores in dependence upon at least one of (i) previously obtained test results, (ii) changes to the product since a previous estimation or regression test has been performed and (iii) information regarding a user. The method includes identifying a candidate test having a confidence score that is below a threshold, in response to the identification of the candidate test, performing the candidate test, and providing, to a user, results of the performing of the candidate test.Type: GrantFiled: March 5, 2021Date of Patent: October 24, 2023Assignee: Synopsys, Inc.Inventors: Boris Gommershtadt, Leonid Greenberg, Ilya Kudryavtsev, Yaron Shkedi
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Patent number: 11797737Abstract: This disclosure describes a method for finding equivalent classes of hard defects in a stacked MOSFET array. The method includes identifying the stacked MOSFET array in a circuit netlist. The stacked MOSFET array includes standard MOSFETs sharing gate and bulk terminals. The method further includes determining electrical defects for the standard MOSFETs, grouping the electrical defects into at least one intermediate equivalent defect class based on a topological equivalence of the electrical defects, grouping the electrical defects in the at least one intermediate equivalent defect class into at least one final equivalent defect class based on an electrical equivalence of the electrical defects, performing a defect simulation on an electrical defect in the at least one final equivalent defect class, and attributing a result of the defect simulation on the electrical defect to additional electrical defects in the final equivalent defect class.Type: GrantFiled: August 12, 2021Date of Patent: October 24, 2023Assignee: Synopsys, Inc.Inventors: Mayukh Bhattacharya, Michal Jerzy Rewienski, Shan Yuan, Michael Durr, Chih Ping Antony Fan
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Patent number: 11790150Abstract: A system and method for placement and simulation of a cell in proximity to a cell with a diffusion break is herein disclosed. According to one embodiment, an integrated circuit is designed to include a first cell that has a first edge and a second edge opposite the first edge. The first cell may also include a diffusion region that extends from the first edge to the second edge with a diffusion break separating the diffusion region. The diffusion break may be spaced away from the second edge by a distance that degrades a metric (e.g., a delay, a slew, dynamic power, or leakage) of a second cell placed next to the second edge beyond a threshold level.Type: GrantFiled: June 14, 2022Date of Patent: October 17, 2023Assignee: Synopsys, Inc.Inventors: Deepak Dattatraya Sherlekar, Shanie George
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Patent number: 11790127Abstract: A method, a system, and non-transitory computer readable medium for aging analysis are provided. The method includes performing stress simulations for a plurality of process, voltage, temperature (PVT) conditions for a circuit, the circuit including one or more devices, extrapolating device level stresses obtained from the stress simulations into device level parameter degradations to a desired circuit age; and performing degradation simulations for the circuit for the same PVT conditions based on the device level parameter degradations. Each degradation simulation for a PVT condition of the plurality of PVT conditions is performed using the device level parameter degradations associated with the same PVT condition.Type: GrantFiled: May 11, 2020Date of Patent: October 17, 2023Assignee: Synopsys, Inc.Inventor: Donald John Oriordan
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Patent number: 11789077Abstract: Disclosed herein are method, system, and storage-medium embodiments for single-pass diagnosis of multiple chain defects in circuit-design testing. Embodiments include processor(s) to select a plurality of a scan chains in a circuit under test and determine presence of at least a first defect in the first scan chain, and a second defect in the first scan chain or in the second scan chain. The plurality of scan chains may include specific scan chains that each have respective pluralities of scan cells. Processor(s) may map the first defect to a first range of first scan cells, and the second defect to a second range of second scan cells. Based at least in part on a failing capture-pattern set, processor(s) may locate the first defect in a first scan cell of the first range, and the second defect in a second scan cell of the first range or the second range.Type: GrantFiled: March 13, 2020Date of Patent: October 17, 2023Assignee: Synopsys, Inc.Inventor: Emil Gizdarski
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Patent number: 11784783Abstract: A method of constructing a waveform from N sampled data captured at N successive points in time, includes, in part, applying the N sampled data, K data at a time, to each of M delayed replicas of a filter that includes K taps so to generate N×M interpolated data. The waveform is then constructed from the N sampled data and the N×M interpolated data.Type: GrantFiled: June 26, 2020Date of Patent: October 10, 2023Assignee: Synopsys, Inc.Inventors: John Stonick, Michael W. Lynch, Dino Toffolon, Ayal Shoval
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Patent number: 11776816Abstract: At least one fin structure may be created on a silicon substrate. Next, a width of the at least one fin structure may be decreased by applying one or more iterations of a self-limiting fin etch process.Type: GrantFiled: December 2, 2020Date of Patent: October 3, 2023Assignee: Synopsys, Inc.Inventors: Victor Moroz, Xi-Wei Lin
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Patent number: 11775363Abstract: A method for auditing a graph-based API includes obtaining a structure describing object types of the API and fields of the object types. A schema graph of the structure is generated including nodes representing object types. The nodes are connected by directed edges representing field resolution between object types. A line graph is generated and includes a node in place of each edge of the schema graph and edges in place of nodes of the schema graph. Frontiers of the line graph are determined, a frontier being subgraph of the line graph such that (1) the subgraph is rooted at a line graph node that represents a field of the API that accepts at least one field argument and (2) the subgraph is a maximal subgraph of the line graph that is disjoint from other line graph nodes that represent fields that accept at least one field argument.Type: GrantFiled: August 5, 2020Date of Patent: October 3, 2023Assignee: Synopsys, Inc.Inventors: Shane Edward Wilton, Kavin Subramanyam, Nathaniel Robert Heydt
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Patent number: 11775716Abstract: A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces of the same random access memory.Type: GrantFiled: January 28, 2021Date of Patent: October 3, 2023Assignee: Synopsys, Inc.Inventors: Arturo Salz, Ching-Ping Chou, Jean-Philippe Colrat, Sébastien Roger Delerse, Luc Francois Vidal, Arnold Mbotchak
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Patent number: 11762283Abstract: Techniques relating to synthesizing masks for use in manufacturing a semiconductor device are disclosed. A plurality of training masks, for a machine learning (ML) model, are generated by synthesizing one or more polygons, relating to a design pattern for the semiconductor device, using Inverse Lithography Technology (ILT) (106). The ML model is trained using both the plurality of training masks generated using ILT, and the design pattern for the semiconductor device, as inputs (108). The trained ML model is configured to synthesize one or more masks, for use in manufacturing the semiconductor device, based on the design pattern (110).Type: GrantFiled: November 23, 2020Date of Patent: September 19, 2023Assignee: Synopsys, Inc.Inventors: Amyn A. Poonawala, Jason Jiale Shu, Thomas Christopher Cecil
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Patent number: 11763056Abstract: A method of simulating defects in an analog circuit design includes, in part, defining a multitude of defect models, defining a defect scope associated with the defect models, and compiling, by a processor, the defect models, the defect scope, and a netlist associated with the analog circuit design. The method further includes, in part, scanning the netlist to identify a multitude of nodes to which a multitude of defects defined by the defect models and the defect scope are applied, injecting the multitude of defects at the identified nodes, and simulating the analog circuit design using the injected defects.Type: GrantFiled: April 20, 2021Date of Patent: September 19, 2023Assignee: Synopsys, Inc.Inventors: Mayukh Bhattacharya, Michael Durr, Mira Tzakova, Beatrice Solignac, Rayson Yam
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Patent number: 11763053Abstract: The independent claims of this patent signify a concise description of embodiments. An emulation control block enables a user to view an entire design in the same phase so that the used can observe and control a halted design in the same logical reference cycle. Both the clock cone and design flops are provided in the state which occurs after the evaluation of cycle K of the reference time. During cycle K+1 of an emulation, the values of derived clocks for cycle K+1 are computed. Moreover, during cycle K+1 of the emulation, the values of the sequential elements are computed based cycle K values of the clocks. When the emulation is halted due to a break, the clock cone is reverted to its previous state. This Abstract is not intended to limit the scope of the claims.Type: GrantFiled: September 25, 2019Date of Patent: September 19, 2023Assignee: Synopsys, Inc.Inventors: Alex Rabinovitch, Bojan Mihajlovic, Xavier Guerin, Manish Shroff
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Patent number: 11763059Abstract: A defect map may be created by merging defects at locations on multiple dies that include copies of an integrated circuit (IC). Layout shapes or nets may be determined that overlap with the defects in the defect map. Next, connectivity between the layout shapes or nets may be determined. The defects may then be grouped into defect groups based on the connectivity between the layout shapes or nets, where each defect group comprises defects that overlap with layout shapes or nets that are electrically connected to each other.Type: GrantFiled: December 17, 2020Date of Patent: September 19, 2023Assignee: Synopsys, Inc.Inventors: Ankush Bharati Oberai, Rajesh Ramesh Sahani
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Patent number: 11764765Abstract: A receiver circuit may include a first stage and a second stage. The first stage may include a first inverter circuit to generate a first signal based on an input signal and a second inverter circuit to generate a second signal based on the input signal. The second stage may determine a logic state of the input signal by combining the first signal generated by the first inverter circuit and the second signal generated by the second inverter circuit.Type: GrantFiled: October 15, 2021Date of Patent: September 19, 2023Assignee: Synopsys, Inc.Inventors: Rahul Gupta, Nitin Bansal, Akhil Thotli, Manoj Kumar Reddy Puli
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Patent number: 11755802Abstract: A method for dependent failure analysis of a circuit design includes obtaining a circuit design comprising a plurality of circuit elements, and generating a first cone of influence and a second cone of influence for the circuit design. The first cone of influence corresponds to a first one or more inputs of the circuit design. The second cone of influence corresponds to a second one or more inputs of the circuit design. The method further includes determining a first shared circuit element of the circuit elements within a first intersection between the first cone of influence and the second cone of influence. Further, the method includes determining a first coupling factor based on the first intersection between the first cone of influence and the second cone of influence, and outputting the first shared circuit element and the first coupling factor to a memory.Type: GrantFiled: December 28, 2021Date of Patent: September 12, 2023Assignee: Synopsys, Inc.Inventors: Shivakumar Shankar Chonnad, Radu Horia Iacob, Vladimir Litovtchenko
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Patent number: 11748553Abstract: A system performs mask rule checks (MRC) for curvilinear shapes. The width of a curvilinear shape is different along different parts of the shape. A medial axis for a curvilinear shape is determined. The medial axis is trimmed to exclude portions that are within a threshold distance from corners or too far from edges. The trimmed medial axis is used to perform width checks for mask rules. The system generates medial axis between geometric shapes and uses it to determine whether two geometric shapes are at least a threshold distance apart. The system performs acute angle checks for sharp corners. The system determines angles using lines drawn from vertices to end points on the boundary of the shape that are at a threshold distance. These angles are used for checking acute angle mask rule violations.Type: GrantFiled: December 23, 2022Date of Patent: September 5, 2023Assignee: Synopsys, Inc.Inventor: Thomas Christopher Cecil
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Patent number: 11740288Abstract: Scan cells of a set of scan chains may be partitioned into at least two control groups of scan cells and at least two observe groups of scan cells. Adjacent scan cells in the set of scan chains may belong to different control groups. Each observe group may include at most one scan cell from each control group, and each control group may include at most one scan cell from each observe group. The control groups and observe groups may be used to perform defect localization on the set of scan chains.Type: GrantFiled: May 31, 2022Date of Patent: August 29, 2023Assignee: Synopsys, Inc.Inventor: Emil I. Gizdarski
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Patent number: 11741282Abstract: Systems and methods for adjusting a digital circuit design are described. For example, the method may include selecting a first path in the digital circuit design. The first path includes a plurality of gates. The method also includes generating a k-hop neighborhood graph of the first path, encoding the k-hop neighborhood graph into a state vector, and applying a machine learning model to the state vector to determine an adjustment to be made on a first gate of the plurality of gates. The method further includes changing the first gate based on the adjustment.Type: GrantFiled: January 19, 2022Date of Patent: August 29, 2023Assignee: Synopsys, Inc.Inventors: Siddhartha Nath, Vishal Khandelwal, Yi-Chen Lu, Praveen Ghanta
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Patent number: 11741287Abstract: The independent claims of this patent signify a concise description of embodiments. Roughly described, a design team prioritizes polygons of a circuit design layout. This information is then encoded into a layout database that is passed to the manufacturing team for correction further processing toward tape-out. The priorities may be used by an engineer to disposition errors found in the layout. For example, a failure may be waived. In another embodiment, the priorities are used during hotspot fixing, a process where failed features are corrected. In hotspot fixing, the priority can be used to make correction tradeoffs in favor of the highest priority features. Priorities are set during the correction to favor fidelity of the higher priority features over the lower priority features. Each embodiment reduces cost, and in some cases, improve final device performance. This Abstract is not intended to limit the scope of the claims.Type: GrantFiled: July 8, 2021Date of Patent: August 29, 2023Assignee: Synopsys, Inc.Inventors: Lawrence S. Melvin, III, Frank L. Ferschweiler
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Patent number: 11742247Abstract: A method of performing epitaxial growth of a source and drain on levels of a complementary field effect transistor (CFET) is provided. The method includes depositing a first blocking material in a vertical channel of an unfinished CFET structure, oxidizing silicon at a surface of an upper level of the CFET to provide one or more SiO2 protective layers, etching away a portion of silicon from a lower level of the CFET to form a lateral recess that is exposed to the vertical channel, and performing silicon epitaxial growth in the lower level of the unfinished CFET structure. Further, after the silicon epitaxial growth on the lower level, the method includes depositing a second blocking material in the vertical channel to cover at least a portion of the silicon epitaxial growth in the lower level, removing the SiO2 protective layer, and performing epitaxial growth on the upper level.Type: GrantFiled: July 9, 2021Date of Patent: August 29, 2023Assignee: Synopsys, Inc.Inventors: Xi-Wei Lin, Victor Moroz