Patents Assigned to SYSTEM INC.
  • Patent number: 12049985
    Abstract: A pressure vessel assembly includes a pressure element storing compressed gas and a shell enclosing the pressure element and capture the compressed gas that permeates from the pressure element. The pressure vessel assembly includes an end fitting extending into a cavity of the pressure element and from the pressure element through the shell. The end fitting includes a stem that extends out from the shell in one direction and into the cavity of the pressure element in an opposite direction and a cap that surrounds the pressure element and the stem at a location external to the pressure element. The pressure vessel assembly includes a retention component sustaining engagement of the end fitting with at least one of the pressure element or the shell below a predetermined pressure threshold.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: July 30, 2024
    Assignee: Noble Gas Systems, Inc.
    Inventors: Christopher T. Kondogiani, Mallory Marie Barrett
  • Patent number: 12050732
    Abstract: In some embodiments, an integrated virtual button module includes a first transducer, a microcontroller, and a first driver circuit. The first transducer includes a transient strain-sensing element and is configured to generate first signals. The microcontroller is configured to obtain first data from the first signals and determine user inputs in accordance with at least the first data. The first driver circuit is configured to receive user feedback data and to generate a first user feedback signal in accordance with the user feedback data. The first driver circuit is electronically couplable to a first actuator. The user feedback data are determined in accordance with at least the user inputs. The first actuator emits a haptic signal and/or a first audio signal when driven by the first user feedback signal. Embodiments of an integrated virtual button system and a method of determining user input and providing user feedback are also disclosed.
    Type: Grant
    Filed: August 23, 2023
    Date of Patent: July 30, 2024
    Assignee: UltraSense Systems, Inc.
    Inventors: Hao-Yen Tang, Hsiou-Yuan Liu, Yonghuan David Ren, Mo Maghsoudnia
  • Patent number: 12050806
    Abstract: A distributed data storage system using erasure coding (EC) provides advantages of EC data storage while retaining high resiliency for EC data storage architectures having fewer data storage nodes than the number of EC data-plus-parity fragments. An illustrative embodiment is a three-node data storage system with EC 4+2. Incoming data is temporarily replicated to ameliorate the effects of certain storage node outages or fatal disk failures, so that read and write operations can continue from/to the storage system. The system is equipped to automatically heal failed EC write attempts in a manner transparent to users and/or applications: when all storage nodes are operational, the distributed data storage system automatically converts the temporarily replicated data to EC storage and reclaims storage space previously used by the temporarily replicated data. Individual hardware failures are healed through migration techniques that reconstruct and re-fragment data blocks according to the governing EC scheme.
    Type: Grant
    Filed: February 21, 2023
    Date of Patent: July 30, 2024
    Assignee: Commvault Systems, Inc.
    Inventors: Anand Vishwanath Vastrad, Avinash Lakshman, Suhani Gupta, Srinivas Lakshman
  • Patent number: 12048586
    Abstract: Embodiments disclosed herein are directed to a stabilization feature configured to be coupled to an ultrasound probe, or similar medical device and grasped by one or more fingers of a user. The user can then manipulate the stabilization feature and probe assembly without requiring any opposing pressure to be applied by the thumb. As such a user is free to use the thumb to operate controls disposed on the probe, or stabilize a skin surface, or the like. The stabilization feature can include a first portion configured to be grasped by one or more fingers, and a second portion configured to engage the probe. Further, the second portion can engage the probe through a sheath to maintain a sterile barrier therebetween. Alternatively, the first portion can be grasped by one or more fingers through a sheath to maintain a sterile barrier therebetween.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: July 30, 2024
    Assignee: Bard Access Systems, Inc.
    Inventors: Bart Peterson, Steffan Sowards, Bradley M. Wilkinson, Anthony K. Misener, Mark Newby, William Robert McLaughlin
  • Patent number: 12050681
    Abstract: Embodiments detect security vulnerabilities, e.g., backdoors, in applications. An embodiment reverses object code of a computer application to generate source code of the computer application. In turn, the generated source code is compared to trusted source code of the computer application to detect a security vulnerability in the object code of the computer application. Embodiments can take one or more protection actions, e.g., sending a notification or preventing execution of the object code, amongst other examples, in response to detecting the security vulnerability.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: July 30, 2024
    Assignee: Virsec Systems, Inc.
    Inventor: Satya V. Gupta
  • Patent number: 12048931
    Abstract: The present invention is directed to a foldable transport container suitable to receive and hold multiple plates with samples in it. The container is comfortable to load, transport and unload. The invention also relates to a strip of material for providing such a foldable transport container. Finally the invention relates to a method for assembling such a foldable container.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: July 30, 2024
    Assignee: Roche Molecular Systems, Inc.
    Inventors: Erich Stiess, Sylvia Dobroszczyk, Jie Pu, Alexander Gaier
  • Patent number: 12052337
    Abstract: Systems and methods are disclosed herein for syntonizing machines in a network. A coordinator accesses probe records for probes transmitted at different times between pairs of machines in the mesh network. For different pairs of machines, the coordinator estimates the drift between the pair of machines based on the transit times of probes transmitted between the pair of machines as indicated by the probe records. For different loops of at least three machines in the mesh network, the coordinator calculates a loop drift error based on a sum of the estimated drifts between pairs of machines around the loop and adjusts the estimated absolute drifts of the machines based on the loop drift errors. Here, the absolute drift is defined relative to a drift of a reference machine.
    Type: Grant
    Filed: September 27, 2023
    Date of Patent: July 30, 2024
    Assignee: Clockwork Systems, Inc.
    Inventors: Yilong Geng, Deepak Merugu, Balaji S. Prabhakar
  • Patent number: 12052092
    Abstract: HA peers can include networking devices that have data planes and control planes that configure the data plane to use status data in a memory for processing network packets of network flows. The HA peers synchronize the status data such that one peer can take over when another fails. When a HA peer is brought up, data plane syncing synchronizes data for new network flows but not existing network flows. A first bulk sync operation synchronizes data for existing flows but not for new flows. A second bulk sync operation can synchronize the data for flows that changed state during the first bulk sync operation. Data plane syncing can sync data for all flows after the first bulk sync operation.
    Type: Grant
    Filed: June 26, 2023
    Date of Patent: July 30, 2024
    Assignee: Pensando Systems Inc.
    Inventors: Balakrishnan Raman, Krishna Doddapaneni, Pirabhu Raman, Sarat Kamisetty, Akshaya Nadahalli, Rathina Sabapathy Sabesan, Prabu Thayalan, Dontula Venkata Ratnananda Ganesh
  • Patent number: 12051180
    Abstract: A method for generating images with high dynamic range (HDR) based on multiple images captured at different aperture values, under different conditions, or at different shutter speeds is applied in a device. The method inputs the original multiple images into a predetermined model and aligns the multiple images. The method further confirms object images that need to be attended among multiple aligned images and obtains a merge weighting for each of the object images, and merges the images for a generated HDR according to the merge weighting of each image. The device utilizing the method is also disclosed.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: July 30, 2024
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Sheng-Yeh Chen, Yung-Yu Chuang, Tzu-Kuei Huang, Nai-Sheng Syu, Yu-Ching Wang, Ting-Hao Chung, Chun-Hsiang Huang
  • Patent number: 12049359
    Abstract: A robotic item retrieval and transport apparatus includes at least one item retrieval mechanism that is minimally exposed while stored and/or engaged in loading or unloading of objects relative to a deck (e.g., upper surface) thereof. Actuators and at least major portions of one or more movable implements are arranged below the deck. Loading and/or unloading of objects may include lateral sliding, such as by pulling the object while it is supported by an extrinsic support surface. At least substantial portions of an item retrieval mechanism may remain outside a central target area of a deck, to provide a unobstructed or minimally obstructed deck surface for holding objects. The apparatus may be used with at least one movable pallet element. A pallet element and/or a retrievable item may include one or more features detectable by a sensor.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: July 30, 2024
    Assignee: Labrador Systems, Inc.
    Inventors: Michael Dooley, Nikolai Romanov
  • Patent number: 12048491
    Abstract: An ultrasound imaging system is disclosed that can include an ultrasound probe including a transducer array configured to acquire ultrasound images, and a console including a processor and non-transitory computer-readable medium having stored thereon a plurality of logic modules that, when executed by the processor, are configured to perform operations including receiving an ultrasound image, detecting one or more targets within the ultrasound image, and generating a visualization from the ultrasound image to center the one or more detected targets within a displayed portion of the ultrasound image. Generating the visualization may include cropping the ultrasound image to center the one or more detected targets within a displayed portion of the ultrasound image. Generating the visualization may include increasing a magnification of a cropped portion of the ultrasound image to center the one or more detected targets within a displayed portion of the ultrasound image.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: July 30, 2024
    Assignee: Bard Access Systems, Inc.
    Inventors: Steffan Sowards, William Robert McLaughlin, Anthony K. Misener
  • Patent number: 12050209
    Abstract: The invention features compact systems and methods for vacuum liquid purification and extraction of a liquid sample.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: July 30, 2024
    Assignee: Fluid Management Systems, Inc.
    Inventors: Hamid Shirkhan, Dirk P. Ten Broeck, Joseph C. Caruso, Yijun Yang, Rashid M. Juma, Thomas G. Hall
  • Patent number: 12048847
    Abstract: This application is generally related to systems and methods for providing a medical therapy to a patient by tracking patient activity and adjusting medical therapy based on occurrence of different types of activities performed by the patient while automatically balancing stimulation program duration.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: July 30, 2024
    Assignee: Advanced Neuromodulation Systems, Inc.
    Inventor: Christopher S. L. Crawford
  • Publication number: 20240250670
    Abstract: A first flip-flop features a first latch having a first circuit configuration with a first transistor having a gate directly linked to an input data node of the first latch, and a second latch having a second circuit configuration with a second transistor having a gate connected to the first transistor. The output data node of the second latch is connected to the second transistor. A second flip-flop having a first latch with the second circuit configuration and a second latch with the first circuit configuration is triggered on the opposite clock edge than the first flip-flop.
    Type: Application
    Filed: April 1, 2024
    Publication date: July 25, 2024
    Applicant: SambaNova Systems, Inc.
    Inventor: Vojin G. OKLOBDZIJA
  • Publication number: 20240249791
    Abstract: An integrated circuit (IC) includes first and scan latches that are enabled to load data during a first part of a clock period. A clocking circuit outputs latch clocks with one latch clock driven to an active state during a second part of the clock period dependent on a first address input. A set of storage elements have inputs coupled to the output of the first scan latch and are respectively coupled to a latch clock to load data during a time that their respective latch clock is in an active state. A selector circuit is coupled to outputs of the first set of storage elements and outputs a value from one output based on a second address input. The second scan latch then loads data from the selector's output during the first part of the input clock period.
    Type: Application
    Filed: April 1, 2024
    Publication date: July 25, 2024
    Applicant: SambaNova Systems, Inc.
    Inventors: Thomas ZIAJA, Uma DURAIRAJAN, Dinesh R. AMIRTHARAJ
  • Publication number: 20240250849
    Abstract: According to one embodiment, a network device may be adapted to operate within a virtual private cloud where network address translation (NAT) is performed through virtual machines and each network address translation is handled differently by a different NAT control logic unit. The network device features one or more hardware processors, and a memory that stores at least a plurality of network address translation (NAT) control logic unit and demultiplexer logic. The demultiplexer logic, when executed, receives an incoming message and, based at least in part on information within the incoming message, determines a selected NAT control logic unit to receive at least a portion of the information within the incoming message. The selected NAT control logic unit handles address translation for routing of a message based on the incoming message to a public network.
    Type: Application
    Filed: April 8, 2024
    Publication date: July 25, 2024
    Applicant: Aviatrix Systems, Inc.
    Inventor: Xiaobo Sherry Wei
  • Publication number: 20240249805
    Abstract: Methods and systems including computer programs encoded on computer storage media, for creating a digital virtual sponsor are disclosed. One of the methods includes receiving an inquiry from a person struggling with addiction. The inquiry is analyzed to determine a response category. At least one appropriate response to the inquiry is determined based on a scripted interaction associated with the response category and a response machine learning model. The at least one response to the inquiry is provided to the person struggling with addiction.
    Type: Application
    Filed: January 30, 2024
    Publication date: July 25, 2024
    Applicant: Addiction Resource Systems, Inc.
    Inventors: Hayes THOMAS, Matthew Charles REEDY
  • Publication number: 20240248853
    Abstract: A heterogeneous processing system and method including a host processor, a first processor coupled to a first memory, a second processor coupled to a second memory, and switch and bus circuitry that communicatively couples the host processor, the first processor, and the second processor. The host processor is programmed to map virtual addresses of the second memory to physical addresses of the switch and bus circuitry and to configure the first processor to directly access the second memory using the mapped physical addresses according to memory extension operation. The first processor may be a reconfigurable processor, a reconfigurable dataflow unit, or a compute engine. The first processor may directly read data from or directly write data to the second memory while executing an application. The method may include configuring the first processor to directly access the second memory while executing an application for reading or writing data.
    Type: Application
    Filed: January 19, 2023
    Publication date: July 25, 2024
    Applicant: SambaNova Systems, Inc.
    Inventors: Arnav Goel, Neal Sanghvi, Jiayu Bai, Qi Zheng, Ravinder Kumar
  • Publication number: 20240248855
    Abstract: A heterogeneous processing system including a host processor coupled to a host memory, a first processor coupled to a first memory, a second processor coupled to a second memory, multiple data transfer resources, and switch and bus circuitry that communicatively couples the host processor, the first processor, the second processor, and the data transfer resources. The host processor is configured to detect an application for execution by both the first processor and the second processor, to select one of multiple data transfer methods for transferring data between the first and second processors, and to configure the heterogeneous processing system based on the selected data transfer method. The data transfer methods include memory extension operation, one memory to memory transfer operation, and two memory to memory transfer operation using at least one intermediate host buffer.
    Type: Application
    Filed: January 19, 2023
    Publication date: July 25, 2024
    Applicant: SambaNova Systems, Inc.
    Inventors: Arnav Goel, Neal Sanghvi, Jiayu Bai, Qi Zheng, Ravinder Kumar
  • Publication number: 20240248860
    Abstract: A heterogeneous processing system and method including a host processor with a host memory having allocated buffer space, first and second processors each with memory, multiple data transfer resources, and switch and bus circuitry that communicatively couples the processors and the transfer resources. The first processor executes a first part of an application generating first data stored into the first memory. A data transfer resource is programed to transfer the first data to the buffer space and to transfer the first data from the buffer space into the second memory. The second processor executes a second part of the application generating second data stored into the second memory. The data transfer resources may include a DMA engine in which the buffer space is DMA addressable. One of the first and second processors may be a reconfigurable processor, a compute engine, or a reconfigurable dataflow unit.
    Type: Application
    Filed: January 19, 2023
    Publication date: July 25, 2024
    Applicant: SambaNova Systems, Inc.
    Inventors: Arnav Goel, Neal Sanghvi, Jiayu Bai, Qi Zheng, Ravinder Kumar