Patents Assigned to Systems, Inc.
  • CLOSE PROXIMITY ALERT MESSAGING SYSTEM AND METHOD
    Publication number: 20100210290
    Abstract: An alert broadcast method includes wirelessly transmitting a first message from a first cellular communication device to a central transceiver. The first message has a characteristic identifying the first message as an alert message. A location of the first cellular communication device is determined. A plurality of second cellular communication devices that are within a proximity of the first cellular communication device are identified. A second message is transmitted from the central transceiver to the second cellular communication devices. The second message is dependent upon the first message.
    Type: Application
    Filed: February 13, 2009
    Publication date: August 19, 2010
    Applicants: Bosch Security Systems, Inc., Robert Bosch GmbH
    Inventors: James W. Riley, Steven Markham
  • Universal hybrid electrical/fiber optic insert cap and hybrid connector and methods
    Publication number: 20100209051
    Abstract: Blank insert caps (pin/socket type) for use in a connector/assembly are partially manufactured or pre-formed to a generic or universal state having a plurality of prospective terminal/contacts. Minimal subsequent processing (performed when desired) configures the blank insert cap into a hybrid insert cap having a desired combination of electrical and fiber optic pin terminals (in the case of pin-style insert cap) or electrical and fiber optic socket terminals (in the case of socket-style insert caps). The blank insert caps include partially formed structures that, when further processed by removal of specific material, are configured into a receptacle for receiving the desired terminal.
    Type: Application
    Filed: December 30, 2009
    Publication date: August 19, 2010
    Applicant: Applied Optical Systems, Inc.
    Inventors: Venkata R. Penumatcha, Vincent A. Wouters, Rodney M. Flower
  • Indicator display module
    Patent number: 7777639
    Abstract: An indicator display module includes a display face for informing an operator of a monitored condition and a housing having first and second ends. The display face is attached to the first end. The housing provides support to electrical components located within the housing. A cover is fixedly attached to the housing and engages the second end of the housing. A seal is positioned within the housing, forming a sealed cavity around the electrical components stored within the housing.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: August 17, 2010
    Assignee: Delta Systems, Inc.
    Inventors: Dennis R. Young, David A. Straka
  • Test generation for low power circuits
    Patent number: 7779381
    Abstract: In the field of integrated circuit design and testing, especially directed towards integrated circuits intended to operate at low power, a method and system are provided for circuit design and simulation and testing for mapping portions of a circuit, such as a power domain or portion of a power domain, to a test mode. Thereby only those portions of the circuit which need to be powered up in a particular test mode are powered up both in the design (simulation) phase and in the actual testing. This conserves power usage during actual testing as against powering up all portions of the circuit, which is not desirable during the testing of the circuit after manufacture. This ensures that the power conditions required to excite and observe any circuit faults during testing exist for the power conditions that are applied during, for instance, manufacturing testing.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: August 17, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vivek Chickermane, James Sage, Patrick Gallagher, Xiaochuan Yuan
  • Generating self-checking test cases from reduced case analysis graphs
    Patent number: 7779374
    Abstract: A method, system and apparatus for constructing a comprehensive test plan using a case analysis graph is provided. Embodiments of the present invention further provide for automatically generating test cases from a case analysis graph and for measuring functional coverage of the test cases. Additional embodiments of the present invention provide for visualizing both the comprehensive test plan and functional coverage data.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: August 17, 2010
    Assignee: Breker Verification Systems, Inc.
    Inventors: Adnan A. Hamid, Arthur D. Flatau
  • Method and system for accessing a remote file in a directory structure associated with an application program executing locally
    Patent number: 7779034
    Abstract: A method and system for accessing a file in a directory structure associated with an application includes a method of accessing a file in a directory structure associated with an application. A request by an application for access to a file is intercepted. The request is redirected to a first isolation environment. A determination is made that the requested file does not exist in the first isolation environment. The request is redirected to a second isolation environment responsive to a determination that the file is identified in an enumeration of a directory structure including a plurality of application files residing on a remote machine. The requested file is retrieved from a file server, responsive to a determination that the second isolation environment does not contain the file and that the file is identified in the enumeration.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: August 17, 2010
    Assignee: Citrix Systems, Inc.
    Inventors: Bradley J. Pedersen, Joseph H. Nord, David Randal Hoy
  • Process for through silicon via filing
    Patent number: 7776741
    Abstract: A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: August 17, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Katie Qun Wang, Mark J. Willey
  • Thermally stable BiCMOS fabrication method and bipolar junction transistors formed according to the method
    Patent number: 7776678
    Abstract: A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed over the emitter layer and remains in place during etching of the emitter layer and removal of the etch mask. The dielectric material layer further remains in place during source/drain implant doping and activation of the implanted source/drain dopants. The dielectric material layer functions as a thermal barrier, to limit out-diffusion of the emitter dopants during the activation step.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: August 17, 2010
    Assignee: Agere Systems Inc.
    Inventors: Arun K. Nanda, Venkat Raghavan, Nace Rossi
  • Biologically absorbable coatings for implantable devices based on polyesters and methods for fabricating the same
    Patent number: 7776991
    Abstract: The disclosure contains a medical article comprising a polymer containing polyesters and, optionally, agents for use with medical articles and methods of fabricating the same are disclosed. The medical article generally comprises an implantable substrate having a coating, and the coating contains a polymer comprising a polymeric product of a reaction comprising a polyol and a polycarboxylic acid.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: August 17, 2010
    Assignee: Advanced Cardiovascular Systems, Inc.
    Inventors: Stephen D. Pacetti, Yiwen Tang
  • Methods and apparatus for spread spectrum generation using a voltage controlled delay loop
    Patent number: 7778377
    Abstract: Methods and apparatus are provided for generating a frequency with a predefined offset from a reference frequency. A spread spectrum generator circuit is disclosed that comprises a voltage controlled delay loop for generating a plurality of signals having a different phase; and at least one interpolator for processing at least two of the signals to generate an output signal having a phase between a phase of the at least two of the signals, wherein the output is varied between a phase of the at least two of the signals to generate the spread spectrum. A spread spectrum having a frequency lower than an applied clock signal is generated using a continuous phase delay increase and a spread spectrum having a frequency higher than the clock signal is generated using a continuous phase delay decrease.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: August 17, 2010
    Assignee: Agere Systems Inc.
    Inventors: Vladimir Sindalovsky, Lane A. Smith, Craig B. Ziemer
  • Dielectric combine cavity filter having ceramic resonator rods suspended by polymer wedge mounting structures
    Patent number: 7777598
    Abstract: A combline filter has a ceramic resonator disposed inside at least one cavity wall. Because the resonator is implemented as a hollow rod, a tuning element may be inserted into an opening on the top of the rod to tune its frequency. A mounting element, inserted into an opening on the bottom of the rod secures its position inside a cavity resonator. Instead of soldering the resonator to the filter's walls, the resonator is supported above a bottom or side wall of the cavity resonator.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: August 17, 2010
    Assignee: Radio Frequency Systems, Inc.
    Inventors: Hamid Reza Salehi, Teppo M. Lukkarila
  • Connectionless configurations for stress testing timing and synchronization in data packet networks
    Patent number: 7778171
    Abstract: A method and system for providing connectionless configurations for stress testing timing and synchronization in data packet networks. Packet traffic of interest is transmitted through multiple interconnected switching nodes such that different packets can be transmitted over different paths through the switching nodes. The nodes can support background traffic in order to generate delays for the packets at each of the switching nodes. By allowing packets to use multiple paths in a single testing configuration, a connectionless packet flow can be utilized for adaptive packet timing recovery stress testing.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: August 17, 2010
    Assignee: Agere Systems Inc.
    Inventor: Paul Stephan Bedrosian
  • Apparatus and method to provide multiple wireless communication paths to and from remotely located equipment
    Patent number: 7778600
    Abstract: A controller may be provided to monitor and record various activities associated with remotely located equipment, e.g. a vending machine or a service vehicle. The controller may also be operable to communicate over multiple wireless communication paths with remotely located equipment, handheld devices and/or a network operations center over multiple wireless networks.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: August 17, 2010
    Assignee: Crane Merchandising Systems, Inc.
    Inventors: Bryan W. Godwin, James M. Canter
  • Systems and methods for tri-column code based error reduction
    Patent number: 7779331
    Abstract: Various systems and methods for tri-column code based error reduction are disclosed herein. For example, a digital information system is disclosed that includes channel detector. Such a channel detector receives an encoded data set and provides an output representing the encoded data set. The exemplary system further includes a decoder that receives the first output and is operable to perform three slope parity checks on the received first output. In turn, the decoder provides another output representing the encoded data set.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: August 17, 2010
    Assignee: Agere Systems Inc.
    Inventor: Weijun Tan
  • Battery charger with temperature control
    Patent number: 7777454
    Abstract: A battery charger integrated circuit with temperature control is disclosed that includes a temperature sensor circuit and a charging current generator circuit. Upon receiving a temperature reading voltage (VDT), the temperature sensing circuit is operable to generate a second reference voltage (VREF) that is a function of the first reference voltage (VREF1). The charging current generator circuit generates and continuously adjusts a reference current (I1) and a charging current (IOUT) according to the second reference voltage (VREF). Whenever the temperature reading voltage (VDT) exceeds the first reference voltage, the temperature sensor circuit is operable to adjust the second reference voltage (VREF).
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: August 17, 2010
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Zhengwei Zhang
  • Method and apparatus for slew rate control
    Patent number: 7777538
    Abstract: Methods and apparatus are provided for controlling at least one of a rise time and a fall time of a signal. A plurality of time shifted clock signals are generated; and a received data signal is sampled using a plurality of parallel data paths, where each of the data paths are controlled by a corresponding one of the plurality of time shifted clock signals. The plurality of time shifted clock signals can be generated, for example, by at least one delay element. The plurality of parallel data paths can be substantially identical and comprise, for example, at least one latch or at least one flip flop. Compensation can optionally be provided for variations in, for example, process corner, supply voltage, aging and operating temperature.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: August 17, 2010
    Assignee: Agere Systems Inc.
    Inventors: Christopher J. Abel, Weiwei Mao
  • Structure and method for fabricating flip chip devices
    Patent number: 7777333
    Abstract: A solder bump structure and an under bump metallurgical structure. An upper surface of a semiconductor substrate comprises a first conductive pad (200) disposed thereon. A passivation layer (202) overlies the upper surface. A second conductive pad (212) is disposed in an opening (204) in the passivation layer and in contact with the first conductive pad. The under bump metallurgical structure (300) encapsulates the second conductive pad, covering an upper surface and sidewalls surfaces of the second conductive pad, protecting both the first and the second conductive pads from environmental and processing effects. According to the present invention, the conventional second passivation layer is not required. Methods for forming the various structures are also presented.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: August 17, 2010
    Assignee: Agere Systems Inc.
    Inventors: Mark Adam Bachman, Donald Stephen Bitting, Daniel Patrick Chesire, Taeho Kook, Sailesh Mansinh Merchant
  • Process control device
    Patent number: D621792
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: August 17, 2010
    Assignee: Fisher-Rosemount Systems, Inc.
    Inventors: Arlyn Miller, Gary Law, Kent Burr, Paul Noble-Campbell, Vincent Lam, Kevin Sloan
  • Mobile phone
    Patent number: D621811
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: August 17, 2010
    Assignee: Chi Mei Communication Systems, Inc.
    Inventor: Yi-En Chen
  • Molded surface of a concrete product
    Patent number: D621960
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: August 17, 2010
    Assignee: Anchor Wall Systems, Inc.
    Inventors: Jimmie L. Mugge, Ronald J. Scherer, David M. LaCroix